Driving forward LCDs in cars
14 January 2008
While large panel LCDs (TV, desktop monitors, notebook monitors) exhibit standardisation and integration, automotive LCD architectures are still based on conventional concepts.
An emerging trend is to employ basic TFT glass and add differentiated features into the display’s timing controller (TCON). Besides external LCD interfaces, there are intra-panel interface options, like the industry standard RSDS (reduced swing differential signalling) bus technology.
A number of graphics source components offer a first level of serialisation that is based on serial data channels for the colour bits with a parallel clock channel. The open, industry-standard FPD (flat panel display)-Link physical layer preserves further interfacing options. This first level of serialisation can then be refined by bridge chips that provide a second level of serialisation onto single pair interconnect.
Conventionally, graphics processing units (GPUs) transmit parallel RGB colour bits aligned to a pixel clock and synchronisation signals. In a remote LCD connection it is not feasible to transport such a parallel bus over more than 20cm to 30cm due to excessive cable thickness, power and electro-magnetic-compatibility issues. The FPD-Link family of Serialiser/Deserialiser (SerDes) chipset transmitters collects up the 18bit of RGB information (in 6bit colour depth mode) plus the three control signals and clock, and converts them into three differential data pairs and one clock pair. The FPD-Link receiver deserialises the data streams, and provides the pixel data and control signals to the TCON on the panel board, which routes and re-formats the signals further towards the LCD glass’s row and column drivers. The chipsets employ the LVDS (low voltage differential signalling) physical layer standard ANSI/TIA/EIA-644A; a low-power interface that provides high line transmission rates, requires little power, generates low noise levels, and is robust. It also rejects common mode noise that is twice the magnitude of the actual differential signal magnitude.
High-resolution panels can be supported over a smaller interface, simplifying interconnect design while supporting varied panel resolutions. The FPD-Link concept evolved to the OpenLDI (LVDS display interface) specification for the transfer of digital display data. To support long cable applications (>10m), an enhanced version of LVDS SerDes is employed. The transmitter’s enhancements are selectable pre-emphasis and a simple, low power DC balancing scheme that opens the eye pattern at the end of long cables. The receiver also offers a cable de-skew function that enables standard twisted pair cables to be used. The LVDS non-DC balanced mode OpenLDI physical layer is backward-compatible and identical to
the FPD-Link physical layer.
A growing number of graphics processors, scalers and low to mid-end FPGAs integrate the FPD-Link physical layer. They distribute a high aggregate data throughput over a number of data channels, which confines the maximum baud rates to moderate speeds, while reducing the design risk of implementing high frequency phase lock loop and clock data recovery circuits. A four-lane (eight-wire) differential interconnect still yields relatively thick and inflexible cabling to route through a car chassis. For cable lengths beyond 5m, potential skew issues between data and clock channels can arise.
An AC-coupled connection provides isolation of shifted ground potentials on the transmit and receive side. Converting to a single lane with embedded clock scheme is logical. For graphics sources equipped with the FPD-Link interface, the DS99R421 from National Semiconductor converts those four non-DC balanced LVDS lanes (3 LVDS Data + LVDS Clock) plus three over-sampled, low speed control bits (OS<2:0>) into a single LVDS DC-balanced serial stream with embedded clock information. This serialisation simplifies transferring the 24bit bus over a single differential pair by eliminating the skew between data and clock paths. The narrower interconnect reduces PCB layers, cable width, connector size and pins. The device integrates the 100U termination resistors at the LVDS inputs and a pre-emphasis signal conditioning function on the LVDS output to boost signals over longer distances.
This user-adjustable feature is controlled through an external resistor and drives up to 10m of shielded twisted-pair cabling at the highest data throughput of 1032Mbit/sec. Internal DC-Balance encoding supports AC-coupled interconnects through series capacitors. The bitmapping of the DS99R421 serial data stream is compatible with the DS90UR124 single lane LVDS deserialiser component.
An optimised interface between the LCD timing-controller and the column driver components needs to support high data throughput while reducing the number of interconnections, power consumption and radiated emissions for less shielding effort. The output drive current is reduced to 2mA. The differential signal amplitude into a typical 100U termination resistor amounts to only ±200mV, more than sufficient for a system internal interface of short to medium reach.
Due to the relatively small signal swing, the edge rates can be designed with moderate slopes during signal transitions, which enables much higher pixel clock frequencies compared to TTL signalling. The RSDS output buffers provide an offset voltage of 1.3V as common mode voltage for the differential signals. The RSDS bus only needs to broadcast RGB colour bits and a parallel clock signal. RSDS uses a 2:1 multiplexing scheme, i.e. on each data channel there are two colour bits, each multiplexed during the rising and falling edge of the clock channel (double date rate). The receiving column driver component does not need an integrated high-frequency PLL circuit, which facilitates its integrating onto or into the glass substrate. The number of bus lines can be halved. For example, in a TTL dual-bus architecture with 6bit colour depth, there are 36 data lines and two clock lines, a total of 38 lines. In an equivalent RSDS architecture, only one bus is needed, consisting of nine differential pairs for data and a differential clock line pair, for a total of 20 lines.
The input signal is usually provided by a serial LVDS data stream from the graphics host side (e.g. the head unit ECU). The LVDS interface is realised in a deserialiser function, which maps the RGB colour bits and control signals (Hsync, Vsync and DE) back into a parallel data format. The TCON routes and re-formats data towards the column and row drivers of the LCD panel.
This TCON combines an LVDS single pixel The differential signal amplitude into a typical 100ohm termination resistor amounts to only ±200mV, more than sufficient for a system internal interface of short to medium reach. Due to the relatively small signal swing, the edge rates can be designed with moderate slopes during signal transitions, which enables much higher pixel clock frequencies compared to TTL signalling.
The RSDS output buffers provide an offset voltage of 1.3V as common mode voltage for the differential signals. The RSDS bus only needs to broadcast RGB colour bits and a parallel clock signal. RSDS uses a 2:1 multiplexing scheme, i.e. on each data channel there are two colour bits, each multiplexed during the rising and falling edge of the clock channel (double date rate). The receiving column driver component does not need an integrated high-frequency PLL circuit, which facilitates its integrating onto or into the glass substrate. The number of bus lines can be halved. For example, in a TTL dual-bus architecture with 6bit colour depth, there are 36 data lines and two clock lines, a total of 38 lines. In an equivalent RSDS architecture, only one bus is needed, consisting of nine differential pairs for data and a differential clock line pair, for a total of 20 lines.
The input signal is usually provided by a serial LVDS data stream from the graphics host side (e.g. the head unit ECU). The LVDS interface is realised in a deserialiser function, which maps the RGB colour bits and control signals (Hsync, Vsync and DE) back into a parallel data format. The TCON routes and re-formats data towards the column and row drivers of the LCD panel. This TCON combines an LVDS single pixel input interface with an RSDS output column driver interface. It resides on the flat panel display and provides the data buffering and control signal generation. The LVDS-based FPD-Link receiver features four data channels, plus one clock channel to provide 24bit colour. The spread spectrum clocking (SCC) function provides a means for reducing EMI by spreading radiated peak energy over a wider frequency band.
An external SSC signal source provides synchronised spread spectrum for RSDS and control signal outputs. The two-wire serial EEPROM interface controls the initialisation of LUT (look up table) registers. If the EEPROM is not present, the internal ROM provides the LUT value. The clock and data synchroniser function delays and aligns data to match the internal data process that includes RSDS skew control. All the data processes need to be aligned through RSDS output and LCD timing control signals. Its RTC (response time compensation) feature will improve the intra-grey level response time of an LCD panel resulting in better motion picture image quality.
The RTC is accomplished through a boost or overdrive voltage that will force the liquid crystal material to respond quicker. The boost pulse is controlled through a combination of an internal or external EEPROM LUT, which contains the boost/overdrive levels, and external memory that acts as a frame buffer. The RTC reference values are the new grey values depending on the difference between the current and previous frames’ RGB grey data.
The RSDS interface transforms CMOS level signals to RSDS for the system clock and RGB colour data. The RSDS skew can be controlled with discrete steps to accommodate different delays to the respective column drivers. The vertical and horizontal LCD timing control block generates the TTL/CMOS level signals for the interface of column and row drivers in the LCD system. All signals are synchronised to the RSDS data clock.
There are about 190 passive components with a 10inch wide-VGA LCD with TTL bus between TCON and column drivers necessary. This is reduced to 101 components using the RSDS bus. The number of PCB layers can be reduced from six with TTL down to four with RSDS. The EMC behaviour also benefits from elimination of wide, parallel TTL/CMOS buses external to the timing controller.
DR. THOMAS WIRSCHEM is product marketing manager, interface and display division, National Semiconductor, Europe.
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