Floorplanning tool for mixed signal
11 March 2008
DATE'08, Munich: Danish start-up Teklatech, announces FloorDirector to speed up adoption of lower geometries.
The software tool stretches clock cycles and shapes power in SoC designs to improve yield and to adapt to the challenges of lower geometries.
Around 30 per cent of designs are in 90nm, estimates Dr Tobias Bjerregaad, CEO, Teklatech. These are incurring on-chip parasitics, supply voltage decreases and noise margins unable to meet the demands of high-speed design, he explains. This will only increase as designers move to 65nm, currently around five per cent of today's designs and then 45nm. For example, resistance and inductance are affected. With faster switching on-chip and high resistance, the dynamic voltage drops.
Dynamic IR drop and supply noise is tackled by FloorDirector intelligently power shaping to flatten power peaks and improve signal and power integrity. It can, claims the comany, produce a 51 per cent reduction in power peaks over baseline EDA flows from other vendors. Addressing dynamic power issues, SoCs can be optimised early in the design phase for power and noise.
Voltage drops and supply noise will lead to unpredictable signal integrity and power integrity and timing effects. Mixed signal SoCs are also susceptible to noise coupling between digital and analogue parts, degrading RF performance. As SoCs are increasingly used in multimedia, DSP, wireless, networking and mobile applications, this degradation can delay product development, missing entry into these competitive markets.
The floorplanning engine analyses the dynamic power signature of system blocks indivdually and identifies initiators of critical voltage drop chains. Shaping techiques and statistical clock timing analysis automates system level IR drop recovery in a scalable clock-level synchronisation.
The software is compatible with third party, Open Access synthesis, routing and verification tools.
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