FPGA joins the house of test

01 January 2007

How FPGA-based reconfigurable I/O helped speed up automated high voltage defibrillator testing for Medtronic.

Traditional automated test systems have relied on off-the-shelf test instrumentation and when test system needs go beyond commercially available capabilities, test engineers have had to develop custom hardware to complete the system. This approach leads to significant extra cost and delays in bringing new products to market. However, a new technology is now available which blurs the line between off-the-shelf devices and custom-designed hardware by combining graphical programming and FPGA-based reconfigurable I/O devices.

According to wikipedia.org: a FPGA (field programmable gate array) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flipflops or more complete blocks of memories.

A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term ‘field programmable’) so that the FPGA can perform whatever logical function is needed.

Reconfigurable I/O
NI (National Instruments) reconfigurable I/O (RIO) technology gives engineers the ability to define their own custom measurement hardware circuitry using reconfigurable FPGA chips and the company’s LabVIEW graphical development tools. The RIO core includes an FPGA chip and surrounding circuitry that enable NI LabVIEW to perform hardware synthesis.

Now, using the same intuitive LabVIEW graphical programming environment used to create the rest of the test system, along with RIO hardware, test engineers can create custom I/O and control hardware without prior knowledge of traditional HDL languages or board-level hardware design. They can create a LabVIEW FPGA block diagram, compile it and download it to a RIO device. The example code in figure 1 simultaneously executes a 32bit counter and pulse generator and a custom control algorithm.

Reconfigurable I/O technology is rapidly becoming an essential part of modern test architectures. These hybrid architectures combine the best of modular and benchtop instruments by having PXI/PCI-based off-theshelf controllers at the heart of the system and using GPIB, USB and LAN/LXI when appropriate. PXI deploys PCI/PCI Express performance in a modular form factor. It supports many more slots than desktop PCs and includes picosecond performance for inter-module timing and triggering.

In ATE systems, the most common form factor used for a RIO device is a plug-in PCI or PXI module that can sit alongside PCI or PXI modular instruments. Whilst RIO technology is currently delivered on individual cards, future generations of modular test instrumentation will incorporate RIO technology on-board.

LabVIEW FPGA and RIO technology can be used in applications requiring custom hardware. When test requirements change, it is simple to modify the block diagram (graphical code) of a LabVIEW FPGA VI (virtual instrument) instead of scrapping the custom hardware that has been built. Example applications that used to require custom hardware and can benefit from FPGA and RIO technology include custom timing and triggering, custom signal conditioning, parallel processing, digital communications protocols, and hardware-inthe- loop (HIL) simulation.

Defibrillator test
The test engineering group at Medtronic was challenged to provide an automated HV defibrillator tester solution with 12 test modules that can independently test up to four different product types while reducing overall test time. Using LabVIEW FPGA and National Instruments RIO hardware, the team dramatically increased module communication speed from 20kHz (parallel port) to 1.7MHz (FPGA), resulting in a
reduction in overall test time.

The previous manual system ran 12 modules synchronously using parallel port communication and only tested one type of HV defibrillator, with a test time of 135 minutes for 12 devices. The new automated system can run 12 modules asynchronously with FPGA digital I/O communication, testing up to four different product types with a test time of 48 minutes for 12 devices. A re-entrant test sequencer and test program independently control each test module so that each device starts testing when directed by the automation device handling system. A test executive PC co-ordinates the automation device handling system and HV defibrillator test system as a whole.

An AeroSpec test automation handling system is responsible for picking a DUT (device-under-test) from one of four input trays, reading the DUT serial number via optical character recognition, loading the DUT into one of 12 test modules, and placing the DUT in one of 12 output trays based on test results. Four different products can be configured on the four input trays and each tray can hold up to 20 devices.

As the system diagram shown in figure 2 shows, the test executive system is the master controller, providing the user interface, directing test module loading and unloading, and instructing the test manager to perform the HV defibrillator test on the device or devices loaded in the test module.

The test executive commands the test automation handler to load a DUT into a test module. Once the DUT is loaded, the test executive commands the test manager to start testing on the specified module. The test executive and test automation handler continue loading the remaining DUTs for the duration of the test sequence, while the test manager commences testing each DUT.

Module communications
Two NI PXI-7811R modules control all communications to and from the test modules and DUTs via serial communications (SPI) and JTAG respectively. Each NI PXI-7811R module runs the same LabVIEW FPGA code as this allows for the most efficient sharing of the FPGA resources.

A test sequencer controls DUT testing by dynamically calling a test case from the test program. Because there are up to 12 independent copies of the test sequencer and test program resident in memory, the system design had to be a compromise between system performance and memory usage. All of the test sequencers and test programs use the same FPGA resources, so the system uses semaphores, or tokens, to control access to each NI PXI-7811R module.

Each FPGA target uses an independent semaphore, to control access. Each FPGA interaction is very short –of the order of a few milliseconds – so this method works very well in allocating the FPGA resources supporting 12 competing programs.

Using the flexibility and parallelism of the FPGA-based RIO devices, coupled with productive graphical development tools like LabVIEW, Medtronic increased the types of HV defibrillators it could test and reduced the overall test time for 12 devices by two thirds. With approximately 600 FPGA interactions per test program per module, the NI RIO hardware handles all communication traffic and maintains independent DUT operations at very high rates. Medtronic now tests defibrillators faster and more efficiently, while still ensuring the reliability required for all medical devices that are designed to save lives.

Next generation ATE systems are increasingly software-defined, bringing together the best of modular and traditional instruments, as well as extending the reach of software down into hardware reconfiguration. FPGAs and reconfigurable I/O are becoming important tools to reduce test system development time and improve performance. With this technology now moving into the instrument itself, custom hardware development may become a thing of the past … in the ‘house of test’ that is.

IAN BELL is technical marketing manager, National Instruments UK & Ireland.


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