FPGAs are moving forward
01 December 2006
Design and verification software provider, Synplicity (www.synplicity.com), believes that the influence of FPGAs has ‘expanded’ with dramatic growth in capacity and performance, as well as a steep reduction in cost. With 80,000 design starts last year, predicted by Gartner to grow to over 110,000 by 2010, the majority of which will include multiprocessor elements, the embedded processing market holds great promise for FPGA use.
As a result, a broader range of applications, using the accelerated, embedded, DSP and software functionalities available, have been found to be suitable for FPGAs. New markets, which take in ASCI designs, explained Gary Meyer (pictured), president and CEO, Synplicity, include those in embedded applications, DSP use, automotive and mobile telephony applications.
In the 1980s, the problem facing FPGA designers was schematic capture, followed by place and route in the 1990s. The next step, according to Meyers is to tackle logic synthesis and them complexity. The deep submicron designs of today require more software to keep the abstraction levels, which is why, according to Meyers, physical synthesis is ‘the next great transition’.
In May, Synplicity announced a collaboration with Xilinx, to focus on productivity for ultra-high capacity 65nm devices. The early access to the device architecture specifications has enabled the introduction of its Synplify Pro synthesis software to support the Virtex-5 LXT 65nm FPGAs, introduced by Xilinx this October
(www.xilinx.com). The FPGAs are the second of the four domain-optimised platforms with built-in PCI express and low-power serial I/Os in the Virtex-5 family. The synthesis software has been optimized for the devices and provides support immediately.
The relationship brings the EDA company an insight into the new devices and processes, explained Meyers, and is the way for software companies to work with silicon manufacturers to make FPGAs workable upon delivery. ‘Working jointly with Xilinx, we can identify tasks and challenges, improving design tools and
design flows, often making them transparent for the user.’ The company can develop synthesis tools at the same time and deliver them on time, instead of separately, trying to mesh the component parts together.
Chief Technical Officer and co-founder, Ken McElvain has a clear vision of the software challenges that new, powerful, 65nm FPGAs will bring. He began by establishing the state of play today, where the levels of abstraction in FPGAs preserve the logic/timing design view of chip design. Mimicking Xilinx’s Steve Trimberger, who quipped ‘At Xilinx, we do deep sub-micron designs, so you don’t have to,’ McElvain believes ‘Designers would also like “we do the design timing, so you don’t have to,” but we haven’t figured that out yet.’ While a lot of information is hidden from the user, it is still essential to know about power distribution and on-chip distribution.
Mentor Graphics (www.mentor.com) has also announced support for the Virtex-5 LXT is now available in its Precision Synthesis release 2006a. The company also announced plans for support to be incorporated in the LeonardoSpectrum tool suite.
FPGAs can experience on-chip variation, leaky transistors, excessive power consumption, decreasing noise margins, signal integrity issues, IR drop effects and soft errors. The effects of deep sub-micron design have been hidden with over-design and timing margins, but McElvain believes that on-chip variation will be the first of these effects to become visible in the next-generation FPGAs designs. The use of clock trees, rather than meshes is dictated by the fact that trees save power and area. However, it is harder to control these elements than in a mesh. Power consumption and process variations all lead to on-chip variation, the effects of which are increasing with the reduced geometries, warns McElvain.
Controlling clock variation requires attention to placement. Less variation in clocks can be achieved, reveals McElvain, by moving the modifying end-point to the same node or clock region of a clock tree. On-chip variations for a clock will eventually exceed clock periods, which could lead to skew-tolerant, latch-based or
asynchronous global communication with local synchronous design, he predicts.
To preserve FPGA design abstraction levels, he says, deep sub-micron problems must be hidden in tools and addressed in software. Hiding deep sub-micron problems in hardware will become too expensive, in terms of die area and performance, as technology scales down in geometries. McElvain, not unnaturally, believes that software will have an increasing role and that physical synthesis is the key.
Another co-operation to promote FPGAs is an agreement the company has signed with Achronix Semiconductor (www.achronix.com) to optimise its Synplify PRO FPGA synthesis tool for the start-up’s
multi-GHz devices.
The move addresses the broader FPGA market, using high-performance design flows and a common interface instead of the traditional choices, VHDL and Verilog language. By combining the resources of the synthesis tool with the programmable devices, the two companies believe that designers can create new types of high-performance FPGAs that have not been achievable to date.
Anchronix is a fabless semiconductor company, established in 2003. It has yet to ship the 2GHz devices, which are described as offering ASIC performance with FPGA flexibility.
The EDA company is optimistic about the future of FPGAs and the industry’s abilities to meet the challenges that FPGAs’ expanding footprints will bring. Physical synthesis will continue to form the basis for future tool development and the company hinted to Electronic Product Design that it is working towards encompassing more DSP, third party IP and customer design formats to flow through its tools. Products to ‘expand the footprint’ and to place physical synthesis as the basis for future tool development early next year.
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