Combining flash
01 December 2007
Renesas' R32C100 32bit microcontroller implements code flash, data flash and Eeprom flash memory.
It offers simultaneous writing and erasure during program code execution and meets exacting requirements for write/erase cycles, data retention and operating temperature range.
Most applications divide a microcontroller’s flash memory into different data areas. The largest area is reserved for program code since its content must allow re-flashing. The flash boot loader program is assigned to a dedicated, protected area, so that it cannot be overwritten during program code reloading. Another area is needed for data that are dynamically generated by the application, and which need to be stored in real-time at regular time intervals or on certain events. This data could be a previously-read switch position, hopping codes of the immobiliser system, error codes for diagnostic purposes or adaptive families of characteristics. Data saved at ignition on/off can generally do with 250,000 storage cycles, whereas dynamically generated data often require up to one million write/erase cycles.
The R32C flash microcontroller uses floating gate flash technology. Flash control functions such as the generation of write/read voltages with the required number of programming pulses, cell voltage verification, time-out and status/error messages are executed in the background using a hardware state machine. Likewise, the flash memory charge pumps and oscillators are integrated on the chip, and support single-voltage operation at 3V to 5.5V at maximum frequency. An error correction that can correct single-bit errors and detect multiple errors is also performed in the background without any performance limitation. This technique uses CRC checksums, generated during data writing. If the checksum of read data differs from the stored checksum, then an error correction or detection will be performed. The additional checksum memory needed for this technique is redundantly available on-chip.
During a memory flashing procedure when writing or erasing data, the CPU outputs the address, the data and the desired function using a register. The state machine handles the rest of the flashing procedure. The program can write data in portions of 2Byte and delete it in blocks. Program flash block size varies between 32kByte and 64kByte. Additionally. two flash blocks of 4kByte each are integrated in the linear address space. They generally serve to store parameter sets, but also support program code execution. All blocks can be locked separately using a special accessing mechanism, so that write protection is ensured for the flash boot loader area.
Besides using the CPU as initiator, the flashing procedure can also be started via the debug interface, and using a synchronous or asynchronous interface in conjunction with I/O pins. Access to write, read and erase procedures is only available using a 7Byte ID code. This ensures that only authorised users can read and manipulate memory contents.
Using this function, the user can update the program code memory on-board and from within an application. An additional flash module is used for the on-chip EEPROM emulation.
The EEPROM flash module is isolated from the program flash memory. It uses a dedicated state machine to generate its own write-erase voltages. The EEPROM flash module is not mapped into the linear address space, but located in a separate area which can only be accessed via status and control registers inside the SFR (special function register). This precludes collisions between the program code flash data bus and the SFR bus, enabling a simultaneous operation of program code flash and EEPROM flash. The background write-erase operation avoids slowing down the CPU by wait states.
The EEPROM flash module is organised in 32Byte segments and supports writing in 2Byte units and erasure of individual segments. A total of 100,000 write-erase cycles are specified for a temperature range
of -40° to +125°C.
The R32C component family equipped with this kind of flash memory features a 32bit architecture with floating point unit, DMA support, and a range of peripheral units and interfaces. Flash memory varies from 128kByte to 2MByte program flash, 2 x 4kByte data flash and from 4kByte to 16kByte EEPROM flash. Some peripheral units were modified specifically for body computer cluster deployment, such as the multi-channel PWM generation with synchronised ADC diagnosis function. This function entails starting up to 32 PWM outputs with an adjustable interchannel delay, and also starting an ADC with an adjustable delay via any analogue channel.
Delayed PWM output avoids simultaneous switching of PWM channels and significantly reduces EMI emissions. In the R32C, the synchronised read-back function is automated using the on-chip IIO (Intelligent Input Output) unit in conjunction with the DMA function and the A/D converter, so that CPU use is minimised. The number of analogue inputs has been expanded to 40 channels in a 144pin package, combined with the number of interfaces keep CPU use as low as possible. This includes six LIN channels for framebased LIN communication under state machine control which only use the CPU for interface initialisation; the remaining LIN protocol activity is executed automatically. All CAN channels contain 32Byte of object memory per channel and limit CPU use using advanced identifier filters and FIFO input buffers.
The R32C microcontroller product family comprises both memory and package variations and versions with Flexray interfaces and a memory protection unit, offering support via standard software and AUTOSAR packages.
MICHAEL LOCH is manager, System Application Group, Automotive Business Unit, Renesas Technology Europe.
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