Serial is the path to triple play success
01 June 2007
High speed serial interfacing on FPGAs is enabling the next generation of triple play communications services
Consumers and businesses alike appear to have an insatiable appetite for voice, video, and computer data communications bandwidth. Potentially, this appetite can now be satisfied through a single high performance network. Yet, despite the commercial promise of tripleplay, substantial obstacles stand in the way of its fulfillment.
The biggest of these is the huge installed base of infrastructure. Replacing it with a completely new network is uneconomic and impractical, yet it is incapable of delivering the performance that high quality triple play service delivery demands.
Transceivers deliver bandwidth
The triple-play challenge drives an incessant demand for ever-increasing bandwidth that has led designers from parallel buses and low-speed transceivers towards serial transceiver-based interfaces. High-speed signals solve many design challenges; they offer new levels of bandwidth and lower overall system cost and power consumption.
Engineers believe that the industry can continue to lower overall cost and power simply by increasing transceiver speed indefinitely. However, going beyond 3Gbit/sec can, in some cases, lead to fundamentally different engineering challenges that make it harder to lower overall system cost and power consumption. The explanation is simple; maintaining signal integrity becomes increasingly difficult at ultra-high speeds, and the extra overhead can sometimes outweigh the benefits associated with increased data rates.
Transceivers in transition
At 1.6GHz, the frequency loss is reasonably manageable, making transceiver implementation at or below 3.2Gbit/sec relatively cost-effective and power-efficient.
However, at 3GHz, the loss becomes significant. Consequently, the implementation of a 6Gbit/sec backplane transceiver requires different feature sets. Advanced techniques, such as decision feedback equalisation (DFE) are likely to be needed to maintain signal integrity, and these advanced capabilities require a different set of optimised features.
This explains why a 3Gbit/sec transceiver typically consumes less than 100mW/channel, whereas a DFE-enabled 6Gbit/sec transceiver consumes at least twice as much power. For applications requiring these advanced features, this extra power consumption is a worthwhile trade-off. However, it becomes advantageous to offer both a low-power 3.2Gbit/sec transceiver and a high-performance transceiver for cutting-edge applications; in essence offering the best tool for the job.
At 5GHz, the signal-to-noise ratio (SNR) becomes negative. In that case, the entire backplane would have to be redesigned with more expensive materials and more sophisticated manufacturing technologies to enable 10Gbit/sec transmission. Consequently, achieving a 10Gbit/sec serial transmission over a backplane incurs a higher cost in terms of die area and power consumption.
Transceivers running at or below 3.2Gbit/sec are at a sweet spot; they are more cost-effective and power-efficient than both parallel interfaces and ultra-high-speed transceivers (running at 6Gbit/sec and 10Gbit/sec) for a large majority of interconnect applications.
This phenomenon has led to two diverging trends in the transceiver market. The first is that bandwidth-hungry applications (such as a backplane interconnect for terabit routers) need 6Gbit/sec and 10Gbit/sec transceivers. These applications continue to push the performance envelope while trading off cost and power.
There are also high-volume applications which are well served by transceivers running at or below 3.2Gbit/sec.
Virtex-5 transceivers
The vast majority of serial protocols run at or below 3.2Gbit/sec; examples include PCI Express Generation 1, Gigabit Ethernet, XAUI, SATA I and II, Serial RapidIO, CPRI, OBSI, and HD-SDI. Many emerging protocols such as JEDEC’s data converter interface and VESA’s DisplayPort also run at these relatively slow data rates. In reality, these established and emerging protocols represent more than 90 per cent of current transceiver applications. Therefore, transceivers running at or below 3.2Gbit/sec are ‘transceivers for the masses’.
Xilinx has developed two different transceivers for its Virtex-5 FPGA family. The Virtex-5 RocketIO GTP transceiver, is designed for highvolume applications and covers data rates from 100Mbit/sec to 3.2Gbit/sec. Targeting the majority of system designers, the GTP transceiver is versatile, easy to use, power-efficient, and cost-effective.
The GTP transceiver is designed to support 8B/10B-based protocols such as the PCI Express Wrapper but also scramblingbased protocols such as SONET. Consequently, the spectrum of applications that can be supported by the GTP transceiver is limitless. In addition, validation and characterisation of the GTP transceiver occurs in application-specific settings to ensure standards compliance. The combination of these design and characterisation approaches ensures the universal appeal of the GTP transceiver.
Tool support
The Virtex-5 RocketIO GTP transceiver wizard offers an intuitive GUI that allows the user to select the GTP, clocking option, FPGA fabric interface, protocol stack, and encoding/decoding mechanism. After selection, the tool generates a GTP wrapper with the necessary features.
The Xilinx ChipScope Analyzer offers self-testing capabilities for the GTP transceiver by leveraging the integrated bit-error-rate tester (IBERT) feature built into the transceiver.
As PCBs become increasingly crowded, transceiver power consumption becomes a critical issue. Therefore, power efficiency was one of the top design objectives for the GTP transceiver. Average power consumption per GTP transceiver is substantially below 100mW. In some cases, pertransceiver power consumption is as low as 60mW. The universal appeal of low-power requirements further enhances the competitiveness of the GTP transceiver for power-sensitive applications.
Triple Play is a potential high-volume application and cost has also become an important consideration. Consequently, Xilinx offers certain solutions in hard logic rather than in LUTs (look-up tables). For example, a hard-coded PCI Express protocol stack includes a physical layer based on the GTP transceiver, a link layer, and a transaction layer. This approach significantly lowers overall solution costs.
Crossing the chasm
The evolution of serial I/O solutions in FPGAs is the result of Xilinx’s high-speed serial initiative, announced in 2002. The aim of the initiative is to accelerate the industry’s move from parallel to highspeed serial I/O by delivering a new generation of connectivity solutions for system designs that meet bandwidth requirements from 3.125Gbit/sec to 10Gbit/sec and beyond.
One of the key objectives in the introduction strategy of these products, with the attending high-speed serial I/O solution packages, was to reach the early adopters and innovators within the FPGA customer base with a viable alternative to custom ASIC and ASSP serial I/O solutions.
Having proven the viability of FPGA-based serial I/O solutions with previous product families, there remained a single, yet extremely important, evolutionary step. To cross the chasm into the mainstream FPGA customer base and truly create equivalency between Xilinx serial I/O solutions and custom solutions required the delivery of fully verified, fully integrated, hard IP-based, turnkey serial I/O solutions.
The new 65nm Virtex-5 LXT and SXT platforms offer the industry’s first FPGA to deliver hard-coded PCI Express Endpoint and tri-mode Ethernet MAC (media access controller) blocks. The Virtex-5 LXT devices address the bandwidth, power, and cost challenges facing equipment vendors working to enable the emerging triple-play services market. The Virtex-5 LXT platform is optimised to enable FPGA designers across a range of applications to benefit from serial connectivity by delivering a comprehensive, compliant protocol solution with the greatest ease of use.
ALIX COXON is marketing manager, Xilinx, EMEA and Gang Sun is senior product marketing manger, High-Speed Serial I/O, Xilinx
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