Next-generation SoC power management
01 March 2007
The next-generation of SoCs will implement advanced forms of DVFS (dynamic voltage and frequency scaling) on the SoC. One way to achieve this is using National Semiconductor’s Advanced Power Controller IP
Power management is an essential part of any electronic system. Traditionally, power management has involved efficiently converting energy from a source (AC, solar panel, fuel cell) to the well-regulated voltage and current level required by the load.
These two factors, conversion efficiency and quality of regulation, have driven the evolution of power management. This began with the emergence of LDOs (low voltage dropouts) and has resulted today in highly sophisticated, multi-mode DC/DC converters with over 90 per cent efficiency.
As regulator efficiency has reached its limits, research has turned towards optimising system efficiency because of the tough requirements of battery-operated energy-constrained portable devices. In such devices, between 30 and 50 per cent of the total energy budget may be consumed by digital processing. Traditionally, digital circuits have relied on the steady improvement of semiconductor processes to solve the power consumption problem. However, the sky-rocketing cost and complexity of designing, verifying and manufacturing using the latest process nodes is putting limits on who and which applications can use the latest processes. Recent industry experience shows simply using the latest semiconductor process does not guarantee low power performance unless power management is taken into consideration from the beginning.
Energy consumption
A complementary, sometimes even alternative, approach to obtaining an acceptable power-performance level is the use of DVFS and the active and passive leakage management of digital SoCs. These techniques can reduce SoC power significantly, especially when combined with fine-grained power management architecture.
The basic equation describing the dynamic and static power consumption of a digital CMOS logic circuit is:
ETASK = (a•C•VDD 2•fCLK + IL•VDD)tTASK
where ETASK = energy used by the digital IC during the task; task energy;
a = activity factor; how large a fraction of the total internal node capacitance of the IC changes state on each clock cycle on average;
C = total switching capacitance inside the digital IC;
VDD = supply voltage of the digital IC;
fCLK = clock frequency of the digital IC;
IL = leakage current of the IC when clock is not active;
tTASK = duration of the task.
This equation assumes rail-to-rail signal swings inside the CMOS IC.
The Advanced Power Controller (APC) allows the optimisation of task energy by dynamically or statically managing supply voltage and leakage current. Supply voltage can be managed using two different techniques: DVS (dynamic voltage scaling) and the more advanced AVS (adaptive voltage scaling). Leakage current can be actively managed using power gating and back-biasing (also known as threshold scaling), passively using multi-VT logic libraries or simply a low leakage (and thus lower speed) semiconductor process option.
APC can also be combined with dynamic frequency management. While the frequency selection algorithm is not part of APC, the controller does have built in support for interfacing with the SoC clock management unit , to allow for variable frequency operation. Frequency scaling algorithms like ARM’s Intelligent Energy Manager as well as proprietary frequency selection methods can be used with APC.
APC functions
APC is available in two soft-IP versions: APC1 and APC2. APC1 is intended for simple SoCs with a single scaled voltage island. APC1 supports the PowerWise Interface 1.0 compliant point-to-point interface for connecting to an external PMIC.
APC2 allows for much more complex SoC power management architecture by supporting multiple parallel voltage and clock islands. Additionally, APC2’s ability to control multiple independent clock domains inside a shared voltage domain is especially significant. This allows low-power operation even when only a limited number of external regulators may be used for system size and cost reasons. The PWI 2.0 bus interface allows APC2 to connect to multiple peripheral devices or even another SoC.
Figure 1 illustrates a dual voltage island SoC and system architecture using APC2:
Table 1: APC1 and APC2 key feature comparison
Feature APC1 APC2
PMIC interface PowerWise Interface 1.0 PowerWise Interface 2.0
Multiple peripherals No Yes
Number of scaled voltage islands 1 1-4
Number of frequency
scaled domains per
voltage domain 1 1-4
Number of HPMs
per clock domain 1 1-4
Frequency levels
supported 8 + clock stop 8 + clock stop
Support for turning voltage domains
on and off Yes Yes
AVS support Yes Yes
DVS support Yes Yes
Leakage management:
Back-bias regulator Yes – on the PMIC
control Yes – on the PMIC or on the SoC
Leakage management:
Multi-VT support Yes Yes
Size (NAND2 Up from 22k depending
equivalent gates) About 11k on SoC configuration
The SoC consists of two main logic blocks in scaled voltage domains, ‘Hardware Accelerator’ and ‘CPU’. From the DVFS point of view any digital function could reside in these domains. Inside each voltage domain a single Hardware Performance Monitor (HPM) for AVS control is shown. If a voltage domain is physically very large, or if significant temporal logic activity variation is expected within the voltage domain, multiple HPMs can be used with multiple clock domains. The clock management unit provides clock signal to both voltage domains as well as to the HPMs.
The four main functional blocks of the APC are shown inside the APC2 block. The control logic block provides host interface (AMBA-APB), CMU interface and interrupts management services. The loop controller(s) manages voltage scaling in AVS mode. APC2 can have multiple loop controllers in case multiple voltage domains are implemented. A frequency-voltage table for each voltage domain is provided for DVS support. The PWI 2.0 master connects the SoC to the PMIC and other peripherals.
Modes of operation
Inside the PMIC are the PWI 2.0 interface logic and various PWIcontrolled normal and AVS voltage regulators. The latter are specifically designed to operate in the fully closed-loop AVSmode. Other functions, such as audio or battery charging, may be integrated onto the PMIC as well.
The APC can implement DVFS operation in two modes: DVS and AVS. In DVS mode a frequency request from the CMU results in APC fetching the corresponding voltage value from the DVS table inside the APC and feeding that value to PMIC. A timer is used to delay the frequency acknowledged to the CMU until the voltage has settled.
The PowerWise AVS mode of operation is indicated by the blue line in figure 1. Frequency change in AVS mode starts with the CMU requesting a new frequency for one of the DVFS domains and setting a new HPM clock for that domain. The APC loop controller then uses the HPM data to determine the required voltage adjustments. It iteratively adjusts the supply voltage until it is at a level sufficient for the new frequency. While this process sounds complicated it provides tremendous benefits in its ability to compensate for process and temperature variation, clock frequency change, static IR drop and PMIC regulator offset. Compared to fixed voltage systems, up to 70 per cent power savings can be achieved when implementing DVFS in AVS mode with the APC2.
Both APC1 and APC2 implement voltage scaling algorithms in programmable hardware. The benefit of this is that voltage scaling becomes software and platform independent, simplifying system integration. Most notably, APC programmability and configurability allows for similar architectural flexibility as a full-custom design, only at a fraction of the time, risk and resource usage usually required for such an effort.
JUHA PENNANEN is marketing director, Advanced Power, National Semiconductor
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