Tools accelerate FPGA development
08 February 2008
FPGA technology can accelerate applications and application development, but design tool support is crucial.
The versatility and intrinsic flexibility of software have seen it dominate as a medium for implementing functionality within electronic devices. There are times, however, when the sequential nature of the processor that executes the software restricts the performance/throughput of a design. Engineers can continue the time-consuming process of optimising code to squeeze more performance from the existing application platform or bite the bullet and redesign the hardware to support faster execution.
One increasing viable alternative is to remove the barriers imposed by fixed hardware and treat hardware as an extension of the software design process. The ready availability of high-capacity programmable devices such FPGAs opens up some intriguing possibilities for embedded developers, including the promise of system design freed from the constraints of a hard-wired and fixed execution platform. However software and hardware development need to be unified to allow embedded designers to seamlessly move between different implementation scenarios.
Descriptive measures
One of the first barriers to be overcome is that imposed by the different languages used to describe hardware and software. At the board level, the language of choice is the schematic diagram. While this provides a concise graphical description of system functionality, it relies on an understanding of the function of the underlying components and how they need to be connected ; not familiar territory for most embedded software developers.
With programmable hardware such as FPGAs, the landscape looks a bit more promising, on the surface. Like C, hardware description languages (HDLs) are programming languages, but the object of HDLs is very different from that of traditional software. HDLs define hardware and are inherently designed to cope with parallelism and asynchronicity. Traditional embedded software is destined to be reduced to a set of instructions that will ultimately be sequentially and synchronously executed on a microprocessor.
The inherent parallelism in HDLs makes it extremely difficult to develop and prove the correctness of a program. Therefore excessive time for simulation and/or formal verification is required, which makes handcrafted RTL expensive.
Also, in a traditional FPGA design flow, electronic circuits are designed at the register transfer level (RTL). This traditional design flow is characterised by a high ‘quality of results’: the design is optimised to make the best use of every resource on the chip. However, the quality of the results is of no importance when the time to achieve the results causes the product to miss its market window, or renders it too expensive to be competitive. Although handcrafted RTL designs can be justified for ASICs that have an enormous up-front NRE cost and ship in high volume, it is too expensive for the majority of embedded systems.
C anything you like!
If schematic-based design is a foreign land and HDL flows are at best counter-intuitive to most embedded developers, then the obvious path to explore is that of extending the reach of C to encompass the creation of both hardware and software. The problem is how to make hardware design accessible through the vehicle of C programming without making development more complicated and time consuming in the process.
C-based hardware design is not a new concept and many companies, including FPGA vendors, offer tools that translate C code into synthesisable RTL. Modern C-to-RTL compilers do succeed to a large degree in extracting significant parallelism from their input. Regardless of the quality of the output, C-to-RTL has not been widely adopted by embedded developers. Many of the current C-to-RTL offerings do not implement full ISO standard C code, the compilers lack maturity of traditional embedded compilers, and legacy code cannot be directly compiled into high performance hardware.
The benefits of C-based design are evident when it is coupled into a system that also manages the hardware implementation portions of the process. To gain the benefits of C-to-hardware compilation and programmable hardware without incurring the time or cost penalties associated with adding complexity to the design flow, embedded engineers need tools that unify software and programmable hardware design.
Abstracting hardware design
The first issue to be addressed to allow engineers to easily harness the reprogrammability of FPGAs to accelerate software applications is providing a simple mechanism to physically connect the processor to the generated hardware. The system also needs to make transparent the process of accessing the generated hardware functions from the software executing on the processor.
Consider a system where the processor is connected to its memory and peripherals through a piece of configurable hardware, essentially a hardware interface implemented in an FPGA, which abstracts the processor interface. By reprogramming the FPGA to change the hardware interface, the system designer could change one processor for another and even move between hard or soft processors without having to modify the rest of the system hardware. From a system perspective all processors would look the same, simplifying the hardware design process.
While the creation of the system platform still falls into the category of hardware design, the possibility opens up to create a generic programmable ‘container’ on the system bus that could be filled with hardware generated on-the-fly by the C-to-hardware compiler. In essence this container becomes an application-specific or configurable co-processor that can be quickly and easily generated to perform any function selected by the software developer.
C functionality
Working within such a unified design system, embedded software developers could selectively and interactively offload C functions to be run as dedicated hardware and the system could take care of generating the necessary RTL and rewriting the software portions of the code to take advantage of it. Developers could quickly test out various implementation scenarios to optimise application execution.
The programmer would gain the ability to automatically generate an application-specific hardware co-processor and add it to the system without ever having to directly edit any hardware.
Design tool vendor Altium has embodied this objective in its Altium Designer system which unifies hardware and software development at the platform level, allowing rapid software/hardware co-design. Software designers can selectively offload C functions to hardware implemented in an FPGA without having to manually modify their application code.
The supplied FPGA-based processors and processor interface cores allow designers to target native Altium or any supported third-party processors, while retaining the full functionality of the design, including the easy connection of FPGA-based peripherals. Altium’s advanced Viper-based unified hardware-software compiler ensure full C-level code compatibility between all processor architectures supported by the system. It can also simultaneously generate both highly-optimised executable code and concurrent hardware for implementation in FPGAs from standard C-code, as well as generating the required code to link the two together at runtime. In practice, this means that developers can simply nominate a function in C-code to be off-loaded from the processor into hardware, while Altium Designer’s unified design environment makes the implementation process fast and transparent.
Software complexity
Adding complexity at a software level will not be a feasible way to carry out embedded design moving forward. Adding more raw processing power to the mix does not solve the problem of increased software complexity. The only way to successfully move forward at the required rate is to approach the design problem in new ways.
Programmable devices have the potential to act as a bridge between hardware design and software development, and provide embedded developers with new ways in which to accelerate application functionality that does not depend on faster processors or handcrafted machine code. These devices can allow designers to raise the level of design abstraction beyond the hardware-software divide and facilitate the creation of embedded device intelligence that comprises both software and programmable hardware elements.
GERARD VINK is associate director, core embedded technology and Rob Irwin is product manager, Altium
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