16Gbit NAND flash memory is in 43nm CMOS
18 March 2008
Toshiba (www. toshiba.co.jp) and SanDisk (www.sandisk.com) have jointly developed a high-density NAND flash memory, fabricated with 43nm process technology. The resulting 16Gbit device improves memory area efficiency by reducing the number of select gates.
Memory cells are grouped and controlled in NAND strings, made up of 64 parallel cells. A dummy word-line cell is positioned at either end of the to reduce the number of select gates and reduce the risk of program disturbance.
Modifying the peripheral circuit design also reduces the chip area, which is approximately 30 per cent less than the same density NAND flash memories, according to the company. It measures approximately 120 sq mm. Adding high-voltage switches to the circuit reduces the number of control-gate driver circuits required
to drive word lines. Further reductions are made by routing the ground buses on the memory cell arrays.
Mass production of the 16Gbit single chip, MLC (multi-level cell) NAND flash memory begins this month at the company’s Yokkaichi facility in Japan. The company plans to introduce 32Gbit versions by Q4 2008.
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