Is it RIP for ASICs?
15 April 2008
There are some things I know for sure. I know the dodo is long gone. But ASICs? Are they as extinct as a sabre tooth tiger? Or more a giant panda, close but hanging in there?
I’m not sure even those in the know, truly know, you know…
ASIC design starts are declining, declares Xilinx’s new CEO, Moeshe Garielov (pictured) as the opening keynote speaker at the GlobalPress Summit in San Francisco this year. So, that’s all I need to know, right? Ahh, but Xilinx is an FPGA company, so he would say that, wouldn’t he? Garielov asserts that ASIC design starts have gone down 40 per cent in the last four years. Yikes, that can’t be good. Expanding on his theme of the future being all about programmability in a programmable world, Garielov contends that the reason for this is that custom chips are rapidly losing steam due to the NRE costs, the expense of masks, the long development cycles and their inflexibility. Chips have to increasingly meet more processing requirements, as social networking and video demand more processing power from the edge to the core, i.e from the enterprise and carrier networks, to consumer products. Programmable logic has moved from the fringes where, five years it acted as a ‘glue technology’ to the centre as customers develop systems around the programmable logic. He went on to say that standard products can be programmable through software, but this compromises the time required to develop the standard product core. True, a low price point may be achieved, but without the right features or the ability to change the feature set. There is a limit to the amount of differentiation through hardware in standard products, he maintains.
While ASICs and ASSPs are in decline, FPGAs are on the up, with iSuppli figures estimating a total market worth of $5billion in 2011, compared to just under $4billion today, or a CAGR of 7.5 per cent.
However, I asked around and Ronnie Vasishta, CEO of eASIC puts another spin on these statistics.
According to Vasishta, the value of FPGA design starts has remained level, at around $4billion to $5billion. Custom IC starts on the other hand garners $23.4billion and ASSPs $60.2billion for the worldwide market. The secret is that while design starts for ASICs may be going down, the revenue for each is increasing.
Well, he would. Can you guess from the company name what eASIC specialises in? Not so much ASIC, as Structured ASIC using its proprietary e-beam technology. This uses a direct-write e-beam, directed through one via above the metal layer to build the original array. According to Vasishta, eASIC is replacing FPGAs, taking its volume FPGA market. Around 30 per cent of customers use a standard product, take IP and put on silicon to sell as their own, despite the 30 to 40 per cent size penalty. However, the majority of traditional ASICs are limited to the IO around the chip, determining its size, rather than the number of gates that can be put in a chip. The resulting device has 10 per cent the power consumption of FPGAs, according to Vasishta, meaning that it does not require cooling as when using several FPGAs in a design.
For Vasishta, the key is to reduce the cost of mass customisation and implementing that customisation into the mainstream in silicon. The company uses a single mask layer, instead of 40, for which an e-beam is used to make an SoC on one layer. He quotes Sony’s Makimoto (he of the Makimoto’s Wave) as saying that the maskless lithography in eASICs single via approach can be customised, bringing affordable customisation.
Abstracting out the design complexity for automated SoC processes should produce ‘right by construction’ design to bring about mass customisation, he asserts.
So, FPGAs bring programming flexibility at lower costs, but ASICs and ASSPs meet the increasing number of sub 100million unit orders and are able to spread the cost of customisation across several customers. New lithographies are also reducing the cost of ASIC, helping to resuscitate the ailing ASIC.
So – hope that’s cleared that up.
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