16bit, 105Msample/sec serial output ADC conserves FPGA I/O pins
18 April 2008
Linear Technology believes its 16bit, 105Msample/sec ADC establishes a new benchmark for digital communication between high speed ADCs and FPGAs.
The LTC2274’s new high speed two-wire serial interface reduces the number of data I/O lines required between a 16bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2.1Gbps, freeing up valuable FPGA pins.
Serial data communications offers simplified layout, and requires less board area for routing, while providing the flexibility to route across analogue and digital boundaries. In noise sensitive applications, the serial interface provides an effective isolation barrier between digital and analog circuitry and serves to eliminate coupling between digital outputs to reduce digital feedback.
The LTC2274 output data is serialised according to the JEDEC serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high speed interfaces including Xilinx’s Rocket IO, Altera’s Stratix II GX I/O and Lattice’s ECP2M I/O. At 2.1Gbps, it is claimed to offer the fastest high speed serial interface of any ADC on the market today. Suitable applications are leading edge communications equipment, multi-channel systems, space-constrained designs, and instrumentation.
For high-sensitivity receiver applications, it provides an internal transparent dither circuit that improves the ADC’s SFDR response well beyond 100dBc for low level input signals. To avoid any interference from the serial digital outputs, an optional data scrambler is available to randomise the spectrum of the serial link. Serial test patterns are also incorporated to facilitate testing of the serial interface. While the LTC2274 may be operated at a maximum sampling rate of 105Msample/sec, the internal PLL may be configured to lock at one of three different sample rate ranges. An on-chip clock duty cycle stabilizer circuit has been implemented to facilitate non-50 per cent clock duty cycles. Separate shutdown pins for the analogue and digital sections are provided to conserve power.
The LTC2274 maintains Linear’s high performance advantages, offering SNR (signal to noise ratio) performance of 77.5dB and SFDR (spurious free dynamic range) of 100dB at baseband. Ultra-low jitter of 80fs RMS enables undersampling of input frequencies up to 500MHz with excellent noise performance. The LTC2274 consumes 1.3W from a 3.3V analogue supply.
The serial output allows it to fit in a 6mm x 6mm QFN-40 package, less than half the size of similar 16bit ADCs with parallel outputs. Pin-compatible 80Msps and 65Msps versions will be released this summer.
Production quantities will be available in July in both commercial and industrial temperature grades. Demonstration boards and samples are available online at www.linear.com/2274.
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