SIP puts ZIP into 16 receiver design
18 April 2008
High-sensitivity instrumentation technology benefits from development of components for wireless basestations.
Some of the latest examples are 16bit ADC (analogue to digital converters) with sample rates over 100MHz.
Interfacing the last down-conversion stage to a high-speed, 16bit ADC requires: language, to deal with the differing terms used in the RF domain compared to the ADC and digital domain; filter design for anti-aliasing combined with differential amplifier design to drive today’s ADC sample-and-hold inputs; and high frequency layout, because even at 100MHz, the high bandwidth front ends of the ADCs pick up noise from
unanticipated sources.
Linear Technology has used SiP technology in the LTM9001, which integrates a 16bit, 130Msample/sec ADC with a fixed gain amplifier. Unlike monolithic ‘buffered’ ADCs, the LTM9001 can interface directly to the IF signal chain.
What’s inside?
The μModule receiver consists of wirebonded die, packaged components and passives mounted on a high performance, four-layer substrate. The first release, LTM9001-AA, is configured with a 16bit, 130Msample/sec ADC. The amplifier gain is 20dB with an input impedance of 200W and an input range of ±250mV. The matching network is designed to optimise the interface between the amplifier outputs and the ADC inputs under these conditions.
There is a second order band-pass filter designed for 162.5MHz, ±25MHz to prevent aliasing and to limit the noise from the amplifier.
The language of RF signal chains uses the 50Ω single-ended signal path as the most basic assumption. Differential signal paths are commonly 200Ω and are easy to accommodate. A traditional ADC input is a
multiple of 50Ω but also a complex, switched-capacitor structure that kicks back current pulses at the sample rate and therefore not easy to use in quick RF calculations. The RF engineer wants to know the input power capability of the ADC in dBm. Power can be calculated using the input voltage range and the input impedance. The input range is specified for a traditional ADC but the impedance is not a fixed, resistive number. The LTM9001 integrates a differential amplifier that presents a fixed, resistive 200W differential input impedance. This presents a more straightforward interface than a switched-capacitor ADC and simplifies the connection to the final stage of the RF signal chain.
The low noise, low distortion amplifier stage provides gain without adding significant noise or distortion to the signal. Despite the low noise of the amplifier, the noise is multiplied by the gain of the amplifier, so higher gain adds noise to the system. However, the input range of the amplifier is proportionately smaller allowing for lower distortion from the preceding components.
Noise abatement
In RF terms, noise figure (NF) is commonly used. NF is the ratio of the output noise power of a device to the portion thereof attributable to thermal noise in the input termination, usually specified at room temperature. In ADC datasheets, noise is specified by its SNR (signal to noise ratio) or similar measurements. SNR is the ratio between the RMS (root, mean, square) amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Amplifiers may specify both but neither term is universally applicable since they infer certain conditions such as the 50Ω impedance implied in the NF measurement or the Nyquist bandwidth implied for SNR. Amplifiers may also specify noise in nanoVolts-per-root-hertz (nV/√Hz) which allows the engineer to do the translation. The LTM9001 specifies SNR with the 200W input impedance and a bandwidth-limiting filter, making chain analysis much easier.
Differential filter design
The next step is to interface the driver to the ADC. In discrete designs, a passive filter network implements an anti-alias filter and matches the amplifier outputs to the ADC inputs. The anti-alias filter between the ADC driver and the ADC inputs limits the wideband amplifier noise and helps preserve the high SNR of the ADC.
State-of-the-art ADCs and drivers are differential and designing filters for differential signals is more complicated than traditional singleended designs. While two single-ended filters can be implemented, the result is less robust than a differential filter. The most obvious difference is that differential designs use a parallel component between the two signal paths instead of a component to ground for each single-ended path. Mismatch of two single-ended filters may introduce differences of phase or amplitude. These differences exacerbate the imperfection of the ADC sample-and-hold circuitry, causing an increase in second harmonic distortion. The anti-alias filter is integrated in the LTM9001 and is a simple two-pole L-C type differential design. It is contained within the LTM9001 so no design is required. The design is characterised and tested with SNR and distortion fully specified over temperature. In the case of the LTM9001- AA, the filter is a 50MHz bandpass centred at 162.5MHz. Other versions, with different filters are in development. Time is saved as applications support from the vendor would typically be required to match the amplifier to the ADC.
Layout
PCB layout has a significant impact on the performance even if the circuit topology and component values are correct. Good practice includes avoiding sharp corners, and keeping the signal paths symmetric and isolated from the clock inputs and digital outputs. A common mistake is to assume that an IF of 140MHz means that high frequency layout techniques are not required. For high performance ADCs, the bandwidth of the sample-and-hold is over 700MHz. High frequency noise can be picked up by the sample-and-hold, reducing the SNR.
Another example is the placement of supply bypass capacitors. A common problem with traditional ADC board layouts is excessive noise due to long traces from the bypass capacitors to the ADC. Good practice is to locate the capacitor close to the supply pin. In discrete designs, the die is wirebonded to the lead frame of the IC package. The bypass capacitor is then slightly further away in the best circumstance. The package size is dictated by the number of pins on its periphery or to adequately dissipate the power of the device. Therefore the bond wires are considerably longer than those in the μModule receiver, 3.5mm compared to 0.8mm (as on the right). The internal bypass capacitors are much closer to the die than is possible in a discrete design. The LTM9001 has a smaller AC footprint, reducing the risk of collecting noise from unintended sources and raising the noise floor.
Both the supply side and the grounded side of the capacitor should be close to the device. Relative to the supply pin, should the capacitor return to the upstream or downstream side of the amplifier? Where should the ADC bypass capacitors return? In some cases a particular supply pin delivers power to the input stage or the output stage of the amplifier, so it is important to return to the upstream or downstream side.
Inductor positions
A discrete, differential bandpass filter will have series inductors in each side of the signal path. Good practice suggests that inductors will be side by side for symmetry. A general rule is that they should be one body width apart, close enough to eliminate the far field effect but not so close as to couple and reduce their effective inductance. This portion of the design is often on the digital board and done by someone not engaged with RF layout on a consistent basis.
The collection of layout, circuit design and high performance components is characterised and tested as a unit, so that a portion of the system requires very few external components.
TODD NELSON is signal chain module development manager, Linear Technology
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