Low jitter generator simplifies video design
13 May 2008
A multi-rate video clock generator delivers HD clock output jitter down to 40psec peak to peak.
The LMH1982 from National Semiconductor provides reference clocks for video ADCs, DACs and FPGA transceivers in video cameras, digital recorders and video editing and post-production equipment. The reference clocks ensure a system’s 3Gbit/sec, HD (high definition) and SD (standard definition) serial digital interface output jitter complies to SMPTE (Society of Motion Picture and Television Engineers) video standards.
Frequencies are selectable for SD (27MHz or 67.5MHz) and HD (74.25MHz, 74.25/1/001MHz, 148.5MHz or 148.5/1.001MHz) resolutions. The device supports NTSC/525i, PAL/625i, 525p, 625p, 720p, 1080i and 1080p video timing.
The level of integration has reduced the device’s 32pin LLP package size to 5mm x 5mm. The device can replace discrete and FPGA phase lock loops with multiple VCXOs (voltage controlled crystal oscillators). Power dissipation is just 250mW. Just a single external VCXO is required to operate the device which can generate two simultaneous SD and HD output clocks and an output top of frame timing pulse. In genlock mode, these output signals can be phase-locked to H and V sync signals applied to either reference port.
The low-jitter output clocks can drive FPGA serialisers without additional clock cleansing. The integrated PLLs synchronise the output clocks to an analogue timing reference from the company’s LMH1981 multi format video sync separator or a digital timing reference from an SDI serialiser. Using an external loop filter offers more configuration options.
Operating voltage is 3.3V to 2.5V. An I2C compatible bus interface is included for programming device registers and reading device status.
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