Virtex FPGA delivers system-level integration
16 May 2008
SAN FRANCISCO: Programmable logic company, Xilinx (www.xilinx.com) has announced the fourth-generation of its Virtex-5 65nm FPGAs.
The five devices add an embedded processor core for processing and high-speed, high bandwidth transceivers, suitable for video, voice and data transport. The FXT has embedded PowerPC 440 processor blocks, high-speed RocketIO GTX transceivers and dedicated XtremeDSP processing capabilities.
The FXT devices include up to 384 DSP slices and 16Mbit internal memory that can be configured to provide over 190GMACs of DSP processing power and 92Tbit/sec of memory bandwidth at 500MHz. The DSP48E slice, common to all Virtex-5 devices raises the level of DSP integration and lowers power consumption over previous Virtex devices. It supports over 40 dynamically-controlled operating modes including multiplier, multiplieraccumulator, multiple adder/subtractor, wide counters and comparators.
The family integrates processing and SerDes components on a single device which will reduce board space and costs in applications where processing performance is accelerating. Application areas include wired and wireless communications, audio/video broadcast equipment, military, aerospace and industrial systems.
The latest addition to the industry’s first FPGAs using 65nm technology is claimed to be 30 per cent faster and with more than 65 per cent more logic capacity than 90nm generation FPGAs. Dynamic power consumption has been reduced by 35 per cent compared with previous generations.
The PowerPC 440 has integrated 32kbit instruction and 32kbit data caches to deliver up to 1,100DMIPS at 550MHz. A 5 x 2 crossbar processor interconnect architecture provides simultaneous access to I/O and memory. There are dedicated master and slave processor local bus interfaces, four DMA ports with separate transmit and receiver channels and a dedicated memory bus interface for highperformance, low-latency connectivity.
Data transfers between the processor, crossbar and soft IP logic are via highthroughput 128bit interfaces to minimise system bottlenecks. The auxillary processor control unit adds further connectivity for coprocessing engines or custom user-defined instructions in video processing, 3D data processing and floating point maths applications. In video over IP designs and wireless basestation reference designs, the FXT family can save cost by 30 per cent and 15 per cent power, claims the company. Integration in itself saves system costs as well as power by eliminating the chip to chip connections.
The FPGA can be used for designing applications with high I/O bandwidths using the low-power RocketIO GTX transceivers which support data rates from 500Mbit/sec to 6.5Gbit/sec. The transceivers consume less than 200mW typical power per channel at 6.5Gbit/sec, using a four-tap DFE receiver equalisation as well as linear equalisation. They also transmit pre-emphais to improve signal integrity at higher line rates. The transceiver blocks have multi-code physical coding sub-layer to support encoding/ decoding schemes, which is estimated to save thousands of logic cells for each channel.
Pin compatibility means that designs can be migrated to the FXT from Virtex-5 LXT and SXT devices to increase embedded processing and serial connectivity.
The devices support XAUI, Fibre Channel, Serial RapidIO, PCI Express 1.1 and 2.0 and Interlaken standards.
The company’s ISE Design Suite 10.1 development tools are available for use with the FPGAs. These include ISE Foundation, Embedded Development Kit, System Generator for DSP, AccelDSP synthesis tool, ChipScope Pro and ChipScope Pro serial I/O Toolkit, PlanAhead design and analysis and ISE simulator. An ecosystem of software development and DSP development environments and debugging tools are also available from third party vendors including Mentor Graphics, Linux, Wind River and Green Hills.
The day after Xilinx announced the new Virtex-5 family, FPGA implementation tool company, Synplicity (www.synplicity.com) announced it has created an automated integration of its Synplify ProFPGA synthesis into the Xilinx Embedded Development Kit. The software already integrates into Xilinx ISE and XtremDSP Development Tools environments as well as Platform Studio, its embedded development tool, using a new script-based flow. Synplify Pro’s synthesis algorithms have been developed to take advantage of the Virtex-5’s six-input LUTs (look up tables); other synthesis technologies are based on four LUT architectures.
The FXT30T and FX70T devices are sampling now, with the FX100T, FX130T and FX200T to be rolled out over the next two quarters. The first production devices are expected Q3 2008.
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