When two tribes go to war, logic wins
24 July 2008
The two tribes are ASICs and FPGAs, of course. Despite reports of the other’s demise, both are holding their ground, writes CAROLINE HAYES
How best not to show favouritism here? Perhaps tackling things alphabetically is the most egalitarian way.
ASICs were the topic of a keynote speech delivered by Ronnie Vasishta, CEO, eASIC (www.eASIC.com) at the GlobalPress Summit in San Francisco earlier this year. The fabless semiconductor company provides Structured ASIC devices which reduce fabrication cost and time of customised silicon devices. The company uses FPGA-like logic cells and via layer customisable routing to develop the Structured ASIC with no mask changes, no minimum order quantity in four weeks. The patented customisation technology uses conventional electronic design flow and standard manufacturing processes in design implementation and device fabrication.
Using only a metal routing technique with a single via layer makes for silicon efficiency, claimed to be as much as 15 times lower in power consumption than FPGAs, with a fraction of the static power consumption at 10s or 100s mW instead of up to 2W for high-density FPGAs.
The company’s Nextreme Structured ASIC technology also eliminates the need for programmable interconnections, with fewer interconnector transistors, resulting in less parasitic capacitance than FPGAs, it claims. This means that the dynamic power consumption of the Structured ASICs is also lower, also typically 10s or 100s mW.
The fewer number of transistors also means a smaller architecture when compared to FPGAs.
As the power consumption is reduced, so the heat dissipation is lower, reducing the expense associated with thermal management. This can mean the difference between using a heatsink with airflow management or not using a heatsink at all.
Bearing in mind that the company was founded by Zvi Or-Bach, the founder of ChipX, specifically to address the emerging ASIC market, it is no surprise to hear Vasishta put forward the view that a change is coming, the advent of affordable mass customisation. We are, he says, at the point of inflection and the ASIC will soon return into mainstream use.
The value of FPGAs remain static at somewhere between $3.75billion to $5billion, compared to ASIC’s healthy $23.4billion and ASSP’s $60.2billion, says Vasishta. The latter shares the technology of ASICs but has more complexities, although they can be used by many customers, so the return on the investments is higher than if sold to a single customer. They represent an increasing revenue stream but designers still battle with the inherent design complexities.
If the rate of ASIC decline continues, there could be as few as 250 design starts by 2030. Yet this prediction is not delivered with gloom. As the design starts go down, the revenue of each goes up.
To bring down the cost of customisation, the company believes that there should not be a unique mask set for each project, nor should there need to be an understanding of the deep sub micron level in the design flow. With this kind of affordable hardware customisation available to ‘the masses’, it can be used by start-ups, universities and research establishments. It is only this way that there need be no limitations on who and how to customise silicon, according to eASIC’s vision.
Sony’s Makimoto (he of Makimoto’s Wave) prophesised maskless lithography. According to Vasishata this has come to pass in the form of the company’s single via which can be customised. The company uses one layer instead of 40 and uses e-beam technology to make an SoC on one layer, drastically reducing fabrication time and cost.
There is also the ability to design through automation, i.e over the web. This allows designers access to the tools that they need. In this way, it is possible to abstract complexity away from each user who until now have had to find out problems each time a chip is built. This ‘right by construction’ design flow is essential for mass customisation to be realised.
Structured ASICs will increase with new ASIC starts, asserts Vasishta, as the cost of customisation reduces, new technologies, such as single mask layers and the tools to design will escalate to 10,000 by 2017, at the cost of ASSP starts. The company’s Nextreme Structured ASIC uses the same platform as ASSPs and incorporates the company’s portfolio of soft IP to customise silicon for individual market segments. ASICs can be up to 5million gates and up to 538k eCells, the company’s own calculation, which
is equivalent to 716k LUTs (look up tables).
Each eCell consists of two three-input LUTs, two NAND gates, where a NAND gate with a three-input LUT allows most four-input logic functions to be implemented, one twoinput multiplexer, one Scan D flip flop, buffers and drivers.
As for memory, the devices can have up to 5.6Mbit block memory, using 32kbit block RAMs, which are tightly coupled with logic blocks for fast access. The block RAMs are user configurable. There is also up to 5.6MByte distributed, dual-port memory, or eRAM. Other features are up to 20 DLLs, 10 PLLs and 32 internal clock domains. Up to 790 user I/Os can be configured into standards and strengths with pull-up/pulldown
options.
FPGA fights back
Which leads to FPGAs themselves. As Structured ASIC companies tell of FPGA design starts remaining static, what do the FPGA companies see as their future? Altera (www.altera.com) has a foot in both camps with recent announcements of a 40nm FPGA and a new Hardcopy ASIC family.
The company is claiming an industry first, with the first 40nm FPGAs and HardCopy ASICs for ASIC prototyping. Both increase densities, with the Stratix IV having up to 680k logic elements, which is twice as many as the company’s Stratix III, which was claimed to be the largest available. The HardCopy ASICs are three times the average size now that transceivers have been added, claims the company, with up to 13.3million gates.
The Stratix IV is manufactured on TSMC’s 40nm process and is available in the GX version, which includes the transceivers and the E (enhanced) series with enhanced memory and DSP resources.
They use the same MultiTrack routing architecture and high performance logic architecture, the adaptive logic module, as previous FPGAs, with added transceivers.
The company’s patented Programamble Power Technology is designed to optimise logic, DSP and memory blocks to maximise the performance while driving down the power elsewhere in the design for powerefficient operation. The company estimates that the FPGAs can deliver 75 per cent power savings at full power.
The transceiver-based ASIC option with the HardCopy IV ASIC family saves development time, as the same Stratix FPGAs can deliver hardware and software co-design and verification before implementing ASIC
production. HCell technology saves power by mapping only the logic needed. Mask layers connect the HCells to Vcc to save power in the design.
Engineering samples of the first GX devices will be available Q4. Customer tapeouts for HardCopyIV ASICs will begin in Q3 2009.
FPGA rival Xilinx (www.xilinx.com) has also added transceivers and an embedded core in the fourth generation of Virtex-5 FPGAs. The five devices, announced at the GlobalPress Summit in April, have embedded PowerPC 440 processor blocks, high-speed RocketIO GTX transceivers and dedicated XtremeDSP processing capabilities.
They include up to 384 DSP slices and 16Mbit internal memory that can be configured to provide over 190GMACs of DSP processing power and 92Tbit/sec of memory bandwidth at 500MHz. The DSP48E slice, common to all Virtex-5 devices raises the level of DSP integration and lowers power consumption over
previous Virtex devices. Over 40 dynamicallycontrolled operating modes including multiplier, multiplier-accumulator, multiple adder/subtractor, wide counters and comparators can be supported.
The family integrates processing and SerDes components on a single device which will reduce board space and costs in applications where processing performance is accelerating.
Although this introduction uses 65nm technology, it is still 30 per cent faster and has more than 65 per cent more logic capacity than 90nm generation FPGAs with up to 35 per cent less dynamic power consumption than previous generations, claims the company.
Pin compatibility means that designs can be migrated to the FXT from Virtex-5 LXT and SXT devices to increase embedded processing and serial connectivity. The devices support XAUI, Fibre Channel, Serial
RapidIO, PCI Express 1.1 and 2.0 and Interlaken standards. The first production devices are expected Q3 2008.
Memory integration
Another approach is to integrate NVCM (non volatile configuration memory) and SRAM, as demonstrated by SiliconBlue (www.siliconbluetech.com) in its 65nm iCE65 FPGAs. The design eliminates external flash PROM to save space and component count in secure designs.
There are four FPGAs initially, which carry their own MVCM to store configuration data to remove the threat of bitstream snooping to make the designs secure.
Configuration is reprogrammable from sources including secure, on-chip, embedded, NVCM or external sources, such as commodity SPI, serial flash PROM or downloaded form a processor SPI.
Operating current is as low as 25μA and has a low dynamic current to maximise battery life. The logic capacity ranges from 2k to 16k logic cells, with an I/O count ranging from 128 to 384.
Volatile and non–volatile versions are available. The FPGAs are available in BGA packages in a choice of sizes from 3mm x 4mm up to 12mm x 12mm.
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