Advancing data processing in embedded systems
24 July 2008
Technology advances at a rapid pace, with companies constantly providing products with more flexibility and additional functionality. These increased performance requirements typically demand intense data processing capabilities.
As an example of this, Apple’s initial iPhone combined a mobile phone, widescreen MP3/video player and a
web browser into a small, lightweight handheld device. This new iteration of the mobile phone is ahead of its predecessors.
The consumer electronics industry benefits from extremely cost-competitive components as well as a large consumer base with a disposable income. With the low cost of entry and increasing functionality of mobile phones, people can afford to buy a new a new model as mobile phone technology continually improves. However, embedded computing architectures aren’t afforded these luxuries. Many embedded systems are employed in long-term applications, with partial technology upgrades being the norm.
System designers need to adhere to strict budgets based on the scope of the project as it stands today, while planning for expansion and an ability to upgrade in the future. Typically, an embedded system needs
to withstand many years of operation, whilst accommodating new technologies that may become available. Designers need to incorporate flexibility, scalability and modularity into system design so as to develop and maintain cost-effective systems that will enable them to adapt their current computing architecture to new requirements as time goes on and the scope of the application changes.
New standards
CPCIe (CompactPCI Express) is the next step up from CPCI (CompactPCI). It enables increased bus performance as well as enhanced data transfer rates and throughput for applications that have
traditionally used a PCI or 3U CPCI bus.
CPCIe takes a new approach to moving data through an embedded system. By employing full duplex, point-to-point, highspeed serial link connections, CPCIe enables multiple bus participants to concurrently transfer data at full speed, instead of forcing data through a common parallel bus connection. Each connection is comprised of one or more lanes with up to 250Mbit/sec available for each lane, resulting in higher data processing capabilities (up to 2Gbyte/sec for an eight-lane link and up to 4Gbyte/sec for a 16-lane link).
Based on the original CPCI standard, the new CPCIe interface uses the existing software of CPCI applications. However, hardware requirements are different since each application will use specific
components. Designers seeking to use CPCIe to enhance existing applications with faster speeds and increase throughput can determine the best strategy for incorporating CPCIe into their systems. For example, considerations such as budgetary requirements need to be made.
Developing a new CPCIe system will be most cost-effective in new applications, since it will require new (and typically more expensive) CPCIe peripheral cards and backplane hardware. Although the designer
gains immediate access to the full capabilities of CPCIe, (including higher transmission speeds for all peripheral card slots), most budgets do not allow for a completely new installation. Most legacy applications should start to incorporate CPCIe solutions as partial system upgrades are performed.
Piecing together
However, there are some pitfalls to including CPCIe in a piece-by-piece fashion. A slot on the backplane is required if a bridge is installed that receives the CPCIe signal from the system’s slot and converts it to
CompactPCI. This slot will hold the bridge board that supports the active logic to convert signals.
To avoid losing a slot in the backplane, a bridge can be installed at the rear of the system, although the bridge clip needed to accomplish this adds cost for duplicating functionality already existing in the latest
chipsets; such as the Intel 945 and 965.
Another solution incorporates CPCI and CPCIe functionality on one board to enable a cost-efficient migration path for upgrading to CPCIe performance in areas where it is needed most. The benefit of this is that it comes without having to scrap or modify legacy CPCI peripheral card applications that still function
acceptably through a CPCI bus. Embedded computing manufacturers are quickly realising the benefits that customers gain by using systems that allow for cost-effective upgrades and future expansion. By collaborating, these companies are developing stronger, more robust solutions for specific applications.
A recent example is the combined efforts of MEN Micro and Schroff that simplifies not only hardware requirements, but also software. The two companies developed a CPCI/CPCIe system that enables a Schroff backplane to work with MEN Micro’s scalable Intel product family, a CompactPCI Express extension board, and an XMC carrier board to provide flexible system configurations (see image). Software re-writes and expensive new software for serial link connections are eliminated, and overall costs drop since the
‘express’ function is used only where high data rates are required; such as in high-end graphics and ethernet operations.
The system in the image depicts an eight-slot hybrid backplane with no bridge or active logic, which allows four slots each for CPCI and CPCIe cards. Both buses are accessed from the same CPU board. The CPCI slots are arranged with 32bit CompactPCI bus and rear I/O on port two. The CPCIe slots include the CPCIe system slot arranged as a four-link configuration connected to three type-2 periphery slots each with one link by four lanes. An additional link with four-lanes directed to the slot at the far right also makes a one by eight-lane configuration possible.
With scalable, packet-based architecture, CPCIe is gaining a significant user base amongst designers that require complex communication, digital and analogue signal processing, and powerful visualisation in
embedded computing systems. The improved performance of CPCIe is beneficial for high-volume data transfer requirements typical in data-intensive computing or graphics applications.
With new CPCIe systems, designers do not have to worry about backwardcompatibility, as all components will meet the standards specifications.
For designers that need to incorporate CPCIe into their current upgrades, there needs to be careful consideration of how to introduce CPCIe elements into an embedded system to ensure that CPCIe remains a costeffective solution.
MANFRED SCHMITZ is president, MEN Micro
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