World’s fastest FPGA
16 September 2008
The Speedster FPGA family is claimed to triple the performance of existing FPGAs, deliver up to 1.5GHz.
The initial FPGA in the family from Achronix is the SPD60, where ‘early engagement’ customers, testing the device ahead of general availability, report its success in applications that require ASIC-like performance, namely, networking, telecommunications, test and measurement and encryption.
The family of FPGAs use the company’s patented picoPIPE acceleration technology that speeds the data through the FPGA fabric. It uses simple handshake protocols to control the data flow and to improve the performance ‘significantly’. Standard RTL for design-entry is used throughout. The picoPIPE is tolerant to variations in supply voltage, which can be used as a power-management tool as power consumption can be lowered by adjusting core supply voltage.
The 10.3Gbit/sec SerDes (serialiser/deserialiser) and the picoPIPE combine to increase system throughput. The integrated DDR2/DDR3 controllers for high-speed memory interface provide the I/O speed to match the core performance. High-speed interfaces that are supported include 40G/100G Ethernet, CEI-6G, 10Gbit/sec backplane, XFI, PCI Express (I and II), XAUI, Serial RapidIO and Infiniband. The DDR2/DDR3 includes a physical layer and controller supporting memory interface speeds of up to 1,066Mbit/sec.
The device is implemented in TSMC’s 65nm G+ CMOS process.
Industry-standard tools and methodologies are available for use with the FPGA, which was announced to the industry on Monday. Designers can leverage existing Verilog and VHL designs. The company’s CAD environment supports the former Synplicity, now Synopsys Synplify Pro and Mentor Graphics’ Precision Synthesis tools for RTL synthesis. The CAD environment provides the tools for physical implementation, performance optimisation, timing analysis, simulation debug and device programming.
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