Direct silicon bonding challenges CMOS
16 September 2008
Toshiba Corporation and IBM unveiled a new technology that challenges CMOS technology for advanced system LSI.
To increase the mobility of the electron, or holes, through device channels or by direct silicon bonding wafers, a CMOS hybrid wafer can be implemented.
The CMOS FET announced in Honolulu (www.toshiba.co.jp and www.ibm.com) was developed by using standard silicon wafers and rotating the plane of the layer by 45 degrees and thinning the direct silicon
bonding layer of the substrate.
Hole mobility in PFETs (positively charged field effect transistors) achieves a higher performance on a substrate. On NFETs (negatively charged FETs) the electric charge mobility deteriorates on a substrate.
This new hybrid-orientation technology, fabricated on a hybrid substrate with different crystal orientation technology is claimed to significantly improve PFET performance without any deterioration in NFET performance.
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