Fast conversion puts satellite in the picture
10 February 2009
New fully space-qualified analogue solutions enable low-power, low-mass, high-performance satellite
modules. Paul McCormack reports.
Broadband telecommunications satellites are required to digitise information bandwidths from 50MHz up to 500MHz necessitating analogue-todigital- converters (ADCs) with sample rates in the 100MSPS+ to 1GSPS+ range.
Resolution/dynamic range and analogue input bandwidth (BW) are also critical parameters. Maximising dynamic range enables high order digital modulation schemes, improved satellite reception in harsh weather conditions and better processing of weak and strong signals. Wide analogue input BW allows direct RF sampling, thereby reducing RF component count, total payload budget and power consumption.
National Semiconductor’s new fully spacequalified PowerWise 8bit to14bit ADCs with sample rates up to 3GSPS and full power analogue input BWs up to 3GHz enable novel communication architectures. Fabricated on pure CMOS processes, these converters enable high throughput systems with wide dynamic range that are power-efficient, compact and lightweight. All ADCs meet total ionising dose (TID) rates of 100krad–300krad, are single event latch up immune to 120MeV/mg/cm2 and have a low single event upset cross section.
The challenge for the space industry
The rapid emergence and worldwide growth in multi-carrier, high-data-rate communication services has become a very important challenge to the space industry. New cellular, satellite, HF, VHF and UHF standards have led to high interest in flexible transceivers that can be configured for multiple application requirements. Because of the number of different standards and variations in use around the world, application-specific hardware is no longer a practical solution to the problem. Instead, the industry is moving towards the development of flexible or software programmable hardware solutions. This requires a thorough examination of the processing requirements and a selection of system components that will provide the flexibility and processing power to meet the needs of several, sometimes vastly different
standards. Proper system architecture and selection of system components requires detailed knowledge of each signal to be processed. Each signal format generally requires unique processing because of differences in BWs, data rates, carrier spacing, modulation and data formats.
System requirements
A transceiver receiver system can be partitioned into three subsystems:
•RF down-converter subsystem: down converts the RF signal to a band that can be processed by the demodulator subsystem
• Demodulator subsystem: Demodulates and digitises the RF or IF signal
•Digital processing subsystem: Application-specific digital processing.
Each of these subsystems must have the flexibility to process the signals of interest and the ability to be upgraded for new signals as they become important.
System architecture
The availability of high-speed and ultra-highspeed ADCs is enabling new demodulator subsystem architecture options. Sampling at high RF frequencies reduces the complexity of the RF subsystem. The ‘L’ and ‘S’ bands within the commercial satellite spectrum, for example, can be directly sampled by gigasample converters such as the ADC08D1520, a 1.5 - 3GSPS ADC with 3GHz analogue input BW. If the received RF signal in a higher band can be mixed directly to one of these bands, and digitised without
further down-conversion, a mixer and frequency synthesiser can be eliminated. This results in a reduction in size and cost and helps towards maintaining the total satellite weight and power budget.
The system designer has several tradeoffs to consider when making the choice between narrowband or wideband architecture. The choice of architecture for the transceiver depends on several factors including; intended system range, maximum transmitter power, required receiver sensitivity, total system size and weight and digital processing power. Essentially the operating bandwidth can be divided among many narrow channels (narrowband – see figure 1) or concentrated into fewer wide channels (wideband – see figure 2). An assessment of space-qualified components shows that higher dynamic range (14bit) mid-speed converters are available for narrowband architectures and lower resolution (8bit to 10bit) ultra-high-speed converters are available for wideband system implementations. The number of channels can be greatly reduced by using a GHz converter but the reduction in a dynamic range due to the lower resolution
may need to be compensated for by increasing transmitter power or by using lower noise RF components. Essentially there is a trade-off to be made between number of TX/RX channels, transmit power, total system size, and cost that must be evaluated on an application-by-application basis.
Useable BW and maximising receiver dynamic range
To maximise available BW and throughput, the analogue components and particularly the ADC must be carefully chosen. There are certain trade-offs between sampling rate, resolution and power consumption that should be considered. The system level architect must make system level architectural and component choices that will result in maximum utilisation of the available spectrum BW.
Nyquist BW is directly related to ADC sampling frequency by the simple relationship:
NyquistBW = FS/2; where FS = ADC sampling speed.
Increasing the Nyquist BW effectively allows more information carriers per ADC channel in the transceiver.
Although there will be some inherent system level limits, generally an ADC with the highest possible sample rate is required. Sampling speed alone is not sufficient. Analogue input BW plays an important role.
The minimum requirement is that the BW allows use of the entire 1st Nyquist zone without signal attenuation, due to gain roll off, for example. It is more desirable if the ADC allows sampling in the 2nd, 3rd and even 4th Nyquist zones. Sampling in the higher Nyquist zones reduces complexity of the RF front end as mentioned above.
PowerWise space-qualified solutions for narrowband systems
The ADC14155 is a high-performance CMOS 14bit 155MSPS ADC with a full-power bandwidth of 1.1GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967mW of power at
155MSPS. A power down feature reduces the power consumption to 5mW while still allowing a recovery time to full operation of only 3.0ms.
A duty cycle stabiliser maintains performance over a wide range of clock duty cycles. The ADC14155 is available in a 48- lead thermally enhanced multi-layer ceramic quad package and operates over the military
temperature range of -55°C to +125°C. It is qualified to meet a TID of 100krad and is single-event latch-up immune to >120MeV/mg/cm2.
PowerWise space-qualified solutions for wideband systems
The ADC10D1000 is the latest advance in National’s portfolio of ultra-high-speed ADC products. Fabricated on a 0.18μm pure CMOS process, it is qualified to meet a TID of 300krad and is single-event latch-up
immune to >120MeV/mg/cm2. The innovative design produces a high 9.0 Effective Number of Bits (ENOB) with a 248MHz input signal and a 1.0GHz sample rate while providing a 10-18 Code Error Rate (CER). The product is housed in a 376 pin Hermetic Ceramic Column Grid Array Package.
The block diagram of the ADC10D1000 is shown in figure 3. It can be seen that there are separate ADC cores with separate sample and hold stages. The ‘I’ and ‘Q’ channels are connected to the individual S/H stages through an input multiplexer. The multiplexer is required for Dual Edge Sampling (DES) mode in which it is possible to connect either input channel to both S/Hs to achieve a doubling in the effective sample rate. In DES mode the external clock is delivered to both converter channels. The clock management circuit adjusts the sampling time delay between channels to exactly half a clock cycle so that the analogue input signal is sampled twice per period of the input clock by consecutive ADC channels. The clock management circuit also monitors, and if necessary corrects the duty cycle of the incoming clock signal. For accurate conversion the internal ADC core must receive a perfect 50% duty cycle clock. The clock duty cycle correction circuit within the clock management module is designed to operate with clock cycles with duty cycles between 20% to 80% and is guaranteed to correct duty cycles within this range to the nominal 50%.
Each converter has a selectable output demultiplexer which feeds two LVDS buses so that the data rate can be reduced for data capture.
Enabling development
Future transceivers require flexible architectures to meet the needs of various cellular and satellite standards as well as emerging signal formats of interest. Advances in space-qualified analogue technology are enabling innovative narrowband and wideband system development. The recent developments in space-grade converter technology presented here allow system designers to make architectural system level trade-offs, previously not possible in the space industry.
PAUL MCCORMACK is National Semiconductor’s European Segment Marketing Manager for Medical,
Military/Aerospace, Test & Measurement
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