How low can it go?
19 May 2009
Variation in 45 nm technologies has been worrying enough, the 32 nm node is coping, but what are the implications for 22 nm and beyond? Already dealing with single atomic layers, will next generation CMOS still be reliable?
Kriti Kohli, the new technical editor at EPD, has written this week’s comment.
The National Microelectronics Institute (NMI), the trade association representing the semiconductor industry in the UK and Ireland, in collaboration with the UK’s nanoCMOS Consortium, hosted the second international conference on CMOS variability last week. The conference was aimed at discussing how design has to change when the underlying technology becomes unreliable, the impact of variability on fabless companies and foundries, and the efforts of the industry to characterise, model and adapt EDA tools for incorporating variability.
A resounding success, the conference was a meeting ground for system, chip and device designers, technology developers, EDA suppliers and wafer foundries to gain crucial insights and explore the challenges created by variability head-on. An inspiring keynote lecture was given by Dr. Kelin Kuhn, Intel Fellow, who put a positive spin on things by reminding the attendees about the massive achievements made in the industry since the 1980s. She discussed the problems faced by the earlier nodes and how they were successfully overcome, for example, the implementation of Optical Proximity Correction techniques to improve lithography resolution. Overall, she concluded: “History demonstrates that variation does not pose an insurmountable barrier to Moore’s law, but is simply another challenge.”
An issue that took centre-stage at the conference was on the definitions of random and systematic variation. This was tackled by the second keynote address, given by Dr. Sani Nassif from IBM. Many agreed with him that when variation is caused by known phenomena, such as wafer edges behaving differently compared to the centre, it can be defined as systematic variability. Conversely, random variability applies to atomistic phenomena driven by scaling, for example, random dopant fluctuations and line edge roughness. However, whilst the process engineer tends to define systematic variability as a problem with known causes that can be modelled and fixed, from the device engineer’s point of view, systematic variation depends on whether or not the phenomenon in question is widely spaced across multiple dies.
Professor Asen Asenov from the University of Glasgow is a leading expert on variability issues in CMOS. He explained that at the heart of the issue is the atomic structure of devices and the granularity of materials. This granularity has become similar to the size of transistors, becoming a major source of statistical variability. The discreteness of charge and the atomicity of matter become especially important for sub-micron CMOS technologies and the International Technology Roadmap for Semiconductors has had to be reconsidered as variability has become a major challenge to scaling and design. For example, the lifetime of bulk MOSFETs has been extended by 4 years to last till 2015 as the timing of CMOS innovation shifts backwards. Professor Asenov also noted that modelling random variation is of utmost concern at the moment as “simple Gaussian models are not sufficient and real distributions tend to be asymmetrical.” He believes that random variability cannot be reduced by fine tuning the technology, and a statistical approach to design will force fundamental changes in the design paradigm.
A topic that generated much interest was on whether statistical or systematic variation is going to be the killer in future CMOS generations. It was a discussion that remained unresolved with IBM, Mentor Graphics, and other speakers concluding that systematic variation will be responsible for yield loss and will eventually become more dominant whilst Professor Asenov, Intel and CSR agreed that statistical variation will need to be addressed more urgently.
Furthermore, the speakers debated on whether EDA tools are ready to cope with variability with Jean-Marie Brunet from Mentor Graphics discussing the current solutions at hand for the design community such as equation-based DRC solutions, model based DFM solutions, and timing/power simulation matching in silicon as possible methods to manage variability. Whilst the rest of the design community supported his views that EDA companies have been working with variability for a while now, the foundry and fabless perspective was not as agreeable. Dr. Nassif commented: “We cannot even do a proper job of predicting the performance of a non-rectangular device with the current TCAD tools.”
One thing that everyone did agree with was that the traditional model of interactions between foundries and fabless design houses needed to be improved. The overall feeling was that no one party will be able to sort out the variability issues, and fabless, foundry and EDA companies will have to work jointly and reprioritise to close the gap between the process and design phase and find a collaborative working model.
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