ADC clock optimisation: A test engineering perspective
25 June 2009
Designing an Analogue-to-Digital Converter (ADC) encode circuit with a respectable 350 fs of jitter is relatively easy, but is this adequate for today’s high-speed requirements?
When testing an AD9446-100—a 16-bit, 100 MHz ADC—at the Nyquist frequency with a 100 MHz sample clock, 350 femtoseconds (fs) of jitter can degrade the Signal-to-Noise Ratio (SNR) by about 3 dB. When the same device is tested at the 3rd Nyquist zone with a 105 MHz analogue input, the degradation can be as much as 10 dB.
To reduce the clock jitter to a more tolerable 100 fs or less, we need to understand what causes the jitter, and how much jitter the ADC can tolerate. Starting with a typical ADC clocking scheme (Figure 1), we will highlight techniques that optimise the clock—and identify commonly used techniques that should be avoided.
What is jitter?
Jitter is probably the most important parameter in developing a good clock circuit. It is a variation in the placement of a clock edge; it will produce timing error, leading directly to errors in conversion accuracy (Figure 2a). Increasing the analogue input frequency increases the slope of the input signal, magnifying conversion error (Figure 2b). The error magnitude is relative—a 0.5-LSB (Least Significant Bit) conversion error for a 10-bit device is equivalent to 32 LSBs of error for a 16-bit device. Jitter thus becomes more of concern as ADC resolution and analogue input frequency increase.
It can be determined how much jitter is acceptable by relating ADC performance to jitter of the encode clock. Equation 1 defines the SNR (dB)—with frequency—of a perfect ADC having infinite resolution (see diagonal lines of Figure 3), while Equation 2 is SNR of a perfect ADC with N-bit resolution (see horizontal lines of Figure 3).
Figure 3 combines these two equations. The intersections show the acceptable total clock jitter for a given analogue input frequency. At low frequencies, the accuracy is limited by the converter resolution. As input frequency increases, a point is reached beyond which the performance of the ADC is dominated by the system’s total clock jitter.
For input frequencies to the left of the intersections, lower jitter is unlikely to be of concern. If the analogue input frequency is near or to the right of an intersection, however, the frequency or resolution must be reduced—or jitter specification improved. In practice, this simplified model, using first-order approximations, loses validity as the analogue test frequency approaches the intersections. To fully understand the effect that clock jitter has on ADC performance, the quantization noise and analogue input amplitude need to be considered in addition to the resolution.
Keeping the jitter out
Anything that modulates the edge transition of the ADC’s clock will introduce or affect jitter. These include crosstalk, EMI (Electro-Magnetic Interference), ground effects, and supply noise.
Crosstalk-induced jitter can occur in any two adjacent traces. If one trace carries a signal, and a nearby parallel trace carries a varying current, a voltage will be induced in the signal trace; if it is a clock signal, the time at which the clock edge occurs will be modulated. Jitter can also be induced by EMI radiation on sensitive signal traces. EMI is produced by switching power supplies, high-voltage power lines, RF signals, and other similar sources. EMI produces similar effects to crosstalk by means of electrical or magnetic coupling that modulates the signal or clock timing.
Bouncing grounds due to switching currents or improper ground connections can also bring about jitter. Switching currents can become large when many gates are switching at the same time. This can induce current spikes on power and ground planes, level-shifting the threshold voltages on clock-circuit or analogue-input signals.
To diminish the jitter caused by these sources, good layout practices and proper circuit partitioning should be employed. It is essential to restrict analogue circuits and digital circuits to their respective domains on every layer.
Improving jitter
Jitter or noise can only corrupt the ADC’s timing when present during the transition or threshold period of the clock. Making this edge (and hence the threshold period) faster by increasing the slew rate reduces the time that noise can be present during the threshold period and effectively lessens the amount of rms jitter introduced.
Thus, minimising jitter means improving the slew rate. One way this can be done is to improve the clock source itself. While high-performance, oven-controlled, low-jitter oscillators can be expensive, available cost-effective oscillators can achieve reasonable performance, even at high input frequencies.
[x-head]Frequency division
If the best oscillator available, based on price and performance, is still not adequate, consider using frequency division and/or filtering. Two parameters affect the slew rate—signal frequency and amplitude. Increasing either of these will increase the slew rate and reduce the system clock jitter to a more desirable number. It is generally easier to increase the clock frequency. Frequency division will then be used to produce the desired converter clock rate, as well as to feed the other stages in the system clock tree.
Clock dividers must contribute, however minimally, to the overall jitter on an absolute basis; but because of the frequency reduction they provide, their output jitter becomes a smaller fraction of the output period, and thus introduces less error.
Reducing phase noise
Total jitter is the Root-Sum-Square (RSS) of the jitter from the clock cleanup circuitry, as well as the jitter in the source and any other intervening components. Thus, if the divider circuit is driven by an extremely noisy source, the full potential of the divider circuit may not be fully realised, simply because the largest jitter term dominates the equation. In this situation, consider using a passive, narrow-band filter between the clock source and the divider circuit.
To illustrate the advantages of filtering, consider a source having a jitter specification of 800 fs. If a clock divider circuit is placed between the source and the converter, the jitter can be reduced to roughly 500 fs even though the divider circuit is capable of much better performance. However, by placing a 5% LC Band-Pass (LCBP) filter between the source and divider circuit the jitter can be reduced to 250 fs.
Five-percent LCBP filters can be easily obtained, but they can be big and expensive. An alternative is to use a crystal-type filter, which with their very narrow pass-band region—usually <1%—can reduce jitter from many sources to less than 100 fs. However, crystal filters add expense and are bulkier than active filters, and have a limited input/output range of 5 dBm to 10 dBm. Pushing them beyond their specified range will result in distortion, possibly degrading the ADC’s SFDR. Finally, some crystal filters may require external components for impedance matching.
It is desirable to clip the signal before it approaches the ADC clock inputs using back-to-back Schottky diodes. This allows the source amplitude to be increased, thus increasing the slew rate, yet keeping the clock’s amplitude at a level compatible with the converter’s clock inputs.
If the clocking system is small or the last stage has short trace lengths, consider using a transformer in concert with the clipping diode. The transformer is passive and won’t add jitter to the overall clock signal. Transformers can also be used to provide gain for the oscillator’s signal voltage, increasing amplitude. Lastly, transformers inherently provide pass-band filtering.
Keep in mind that not all diodes will perform equally. Read the specifications carefully and pay particularly close attention to the dynamic resistance and total capacitance specifications. Diodes with low R and C values can improve clipping speed and maintain performance.
Jitter reduction in clock hardware interfaces
There are many circuits and solutions that can be used when interfacing to the ADC’s clock input pins. A valid expectation is that each active component (oscillator source, driver or fanout gate, divider, etc.) in the signal chain will increase the total amount of jitter presented to the ADC’s clock input pins.
The type of clock gates chosen is also worth noting. Simple logic gates and FPGAs are probably not the best choice when seeking to obtain good performance at high analogue input frequencies. It is best to carefully read the data sheets of candidate devices and understand the pertinent specifications, such as jitter and skew. This is especially important when they are to work with sources that have extremely low jitter.
Rob Reeder, Wayne Green, and Robert Shillito work for Analog Devices
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