Xilinx targets evolution of FPGA design
25 June 2009
Targeted design platforms enable FPGA design based on user-specific configurations. Xilinx now offers design tools that can deliver up to 50% shorter development cycles.
Engineers creating FPGA-based systems-on-chip face various challenges with design teams requiring different types of tools. For example, whilst the logic designer is interested in developing and simulating RTL code, the embedded software developer prefers the C/C++ environment for development and debug. Recognising the different types of users and with the aim of addressing the needs of all the disparate designers, Xilinx released the ISE Design Suite 11.1, an FPGA design solution with domain-specific design flows and tool configurations for logic, DSP, embedded processing and system-level design.
The targeted design platform is Xilinx’s attempt to ‘enable innovation while maximising productivity.’ Split into four key elements: the base platform for logic designers, the domain-specific platform for embedded, DSP and connectivity applications, the market-specific portions touch into video specific IP and custom tools, and customer design which is focused on differentiation. Mark Goosman, Senior Product Marketing Manager of Xilinx Design Tools, explained: “Xilinx customers have cut their development cycles from one-and-a-half years to about nine months, we’ve got to be able to leverage the existing markets. That is the value of targeted design platforms.” What Xilinx has done is to take previously available tools, and made them available in user defined applications thereby facilitating faster development cycles and maximising productivity.
The ISE Design Suite 11.1 comes in various editions as a way of matching tools to user profiles. For example, the Logic Edition consists of the ISE Foundation, which is Xilinx’s flagship design product, in addition to other development options such as the PlanAhead Floorplanner for pin planning and the Chipscope toolkit that verifies design as it is running. Comparitively, the DSP Edition contains the Logic Edition along with all the products that support MATLAB and Simulink for developing algorithms or implenting in Verilog/VHDL. Other editions are the Embedded Edition for the development of embedded design in FPGAs, and the System Edition that stitches all the other editions together. For the embedded software developer, a standalone product is also available, one which contains the software development kit including debuggers, compilers but comes with no additional tools.
What differentiates version 11.1 from previous releases of the ISE Design Suite is the focus on targeted design. This results in improvements specific to each user-profile. For example, “from feedback, we have found 20% of embedded designs now require more than one processor. Previously it had been difficult in the Xilinx flow to include both processors and this has been improved in ISE 11.1,” said Goosman. The DSP edition includes enhancements to the System Generator where “as part of streamlining of the methodology, when a user accesses code, it is automatically brought up in SDK,” added Goosman. Additionally, enhancements to AccelDSP, an algorithm synthesis tool, delivers ‘2x higher performance for common low-level type of functions’ in an environment designers are familiar with. Tom Feist, ISE Design Suite Senior Marketing Director said: “ DSP designers don’t have to worry about RTL etc. it has all been rammed behind the scenes for them.” System integrators benefit from the ISE 11.1 as the automatic incorporation of constraints into the implementation flow makes it easier to work with different domains. “It manages all constraints and improves interoperability between designers,” added Feist.
Other performance related improvements compared to previous releases are on cutting development times through, on average, 2x faster runtimes in Place and Route algorithms and 4x faster simulation. The 2nd generation SmartGuide “increases productivity late in the design,” said Goosman. XST synthesis runs 1.6 times faster resulting in reduced synthesis runtimes. Additionally, Xilinx claims ISE 11.1 can provide 10% better dynamic power via Place and Route optimisations and a reduction in memory requirements by 28%.
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