Packet power
25 August 2009
SRAM devices support high speed processing for packet lock-up and packet buffer applications.
In 1999, the QDR co-development team was created to define a new family of SRAM architectures for high-performance communications applications. The QDR co-development team currently consists of Cypress, Integrated Device Technology, NEC, Samsung, and Renesas. These companies cooperate in the development of the QDR family of networking SRAMs.
Renesas announced the 72 Mbit Quad Data Rate II+ (QDR II+) and Double Data Rate II+ (DDRII+) high-speed SRAM product family for use in high-end routers and switches in next-generation communication networks. These SRAM products achieve the industry's fastest operating speed and are compliant with the QDR Consortium industry standard. The new family also includes 72 Mbit QDRII and DDR II SRAM devices.
QDR SRAM and DDR SRAM adopt a DDR technique where, while acquiring the address and control signals from the processor or controller in synchronisation with the system clock, the SRAM also writes or reads data signals in synchronisation with both the system clock and an inverted system clock signal. As a result, these devices can achieve transfer rates that are twice those of earlier synchronous SRAM. Furthermore, since the input and output pins are separate and isolated, read and write operations can be performed at the same time. This allows data to be transferred with efficiency and makes it possible to achieve data rates that are four times those of earlier synchronous SRAM devices.
For these products, Renesas greatly increased operating speeds while maintaining low-voltage operation by utilising an advanced 45 nm fabrication process. The QDRII SRAM products achieve an operating speed of 333 MHz, and the QDRII+ SRAM products also provide an operating speed of 533 MHz. These devices can support high-speed processing for packet look-up and packet buffer applications in high-end routers and switchers that support 10G, 40G, and higher multi-layer communication systems.
Renesas will provide products that support three data I/O widths (9, 18, or 36 bits) and two burst lengths (2 or 4 words). In addition, Renesas will also provide products that feature a built-in ODT (On-Die Termination) function that significantly reduces the signal quality degradation that can occur during high-speed operation.
With the ever-growing popularity of the internet, transmission speeds and the amount of traffic being sent to communication equipment continues to increase, with data rate speeds now exceeding 40 Gbits/second. Checking data destinations and managing data packet traffic in the high-end networking equipment is driving the demand for high density memory capable of high speed performance. Furthermore, the complexity of data continues to increase with video, voice, and data applications, requiring even larger memory capacities.
Renesas currently provides a broad range of SRAM products for industrial applications and for cache memory in UNIX servers and workstations, as well as 18 Mbit Network SRAM and 36 Mbit DDRII and QDRII SRAM for communication equipment.
These products are available in all combinations of burst lengths and bit widths, and the standard HSTL (High-Speed Transistor Logic) interface is used for ultra high-speed synchronous SRAM. The package used is a 165-pin plastic FBGA with a 15 mm × 17 mm size that features thermal dissipation characteristics and is suitable for high-density mounting.
These products are RoHS Directive-compliant and lead-free versions are also available. The QDR pin configuration will support migration to densities of up to 288 Mbits in the future. In addition, FBGA package products support the IEEE standard test access port and boundary scan architecture (IEEE std. 1149.1-1990) that allow interchange connection checking during module mounting to be conducted at the board level.
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