Reducing energy consumption through efficient design
28 September 2009
Richard Zarr examines several methods that can improve power consumption and reduce thermal requirements for devices.
Energy consumption is a hot topic today, not only for regulatory requirements but for simply reducing the thermal footprint of a device. Improving the efficiency of a power converter from 93% to 95% may help a product’s overall energy consumption, but in the scheme of a system design much larger gains can be found through architectural improvements.
Systems designers are feeling the pressure today to look for ways to reduce the energy consumption of new products. In many cases engineers start at the front of their power connection and examine the efficiency of their power supplies. The drive to improve the conversion efficiency is highlighted by many new standards such as 80Plus In a world where PC power supplies vary from 60% to over 90% efficient, it makes sense to drive every manufacturer to a higher level.
However, in many products engineers have already upgraded power supplies to very high efficiency levels. Looking for more exotic conversion methods to extract a few additional percent of efficiency may not be the best place to look for improvements. There are system level decisions that could greatly improve the overall energy efficiency of a product. For example, a great deal of engineering may be involved in improving a highly efficient car engine to produce more torque with less fuel. A simpler approach may be to switch the car body to a lighter material reducing the overall vehicle weight and dramatically improving mileage.
Stepping back
Periodically, designers are too close to the problem and may need to take a step back to consider the system. Are there other areas that affect power consumption? For example, many systems are dependant on complex ASICs or DSPs to provide the system functionality. Analogue signal path subsystems are used to convert real-world input into bits for processing inside a digital core. By moving functionality back into the analogue domain, energy consumption can be reduced by off-loading digital blocks.
An example of this might be found in a wireless, battery powered alarm system. A designer may elect to provide an analogue filter and envelope detector that listens for the audio signature of glass breaking. This allows the rest of a digital based sensor to “sleep” while the analogue subsystem continuously monitors for intrusion. Once the signature is detected, the processor can be powered up and send a report to the master console. In this scenario the digital core which consumes most of the power is in stand-by and only the low power analogue is powered up greatly extending battery life.
Designers of personal mobile devices such as phones constantly look for methods to extend the operating time of the device with ever shrinking form factors (and batteries). Looking to improve power converter efficiency from 94% to 96% may provide an additional 10 minutes of operation, but looking closer at the system reveals larger power consumers that can be addressed.
One area of interest is the RF power amplifier. This part of the system is only used when the handset is communicating back to a base station, however it is one of the largest consumers of energy in the device. In early mobile phone designs the PA was simply connected directly to the battery to ensure maximum power operation. Today, more sophisticated methods are used where RF power measurements are made at the power amplifier output and a switching power regulator is used to control the PA supply to ensure the proper RF output level. This closed loop system greatly reduces energy consumption when the phone is actively communicating. This is an architectural change that dramatically decreased power consumption and improved talk-time.
Digital processing and shrinking cores
Most digital systems are built on standard CMOS processes which use energy as a function of the square of the supply voltage plus leakage. As the CMOS processes decrease in geometry, the leakage component grows due to limitations in the dielectric materials and the physical dimensions of the gate oxide. New high permittivity materials such as Hafnium based dielectrics decrease the electrical depth while maintaining the physical thickness. These materials can also help limit gate leakage by limiting tunnelling which occurs as the oxide layers are made thinner.
While high-K dielectrics may be the future for CMOS geometries below 65 nm, there are still methods for reducing energy consumption in all CMOS processes. One that has been used for quite a while is called Dynamic Voltage Scaling (DVS) and requires the digital core to play an active role in monitoring the activity of the system. If the load on a digital core varies, then it might be possible to slow the clock in various sections of the system. At the same time, the supply voltage to these sections can be reduced since the timing no longer requires the higher speeds. By looking back at Equation 1 it can be seen that the dynamic component is dramatically reduced as well as the leakage when the supply voltage is reduced.
DVS works well to reduce the power consumption in systems that benefit from varying task loads. However, this technique does nothing for process or temperature variation. As in the RF power amplifier example above, a method that could track the silicon performance and automatically adjust the power supplies would be ideal. This method could reduce power (and heat) by optimising the supply voltage to every individual component – not simply the worse case distribution.
One technology that does precisely this is called Adaptive Voltage Scaling (AVS) pioneered by National Semiconductor in early 2000. Again, this technology is an architectural improvement to the methods used to power large digital ASICs. Traditionally, timing closure for a design is done at several corners that define the worse case process and temperature for a design. Engineers need to know that in all conditions (even those that will never be seen by a product) the digital timing will be met and the system will operate properly.
AVS uses embedded digital IP called a Hardware Performance Monitor (HPM) that supervises the silicon performance and continuously reports back to a system controller. The controller (called the Advanced Power Controller or APC) determines whether the process is running slow or fast for the current system requirements. If the process is slow, the APC can command an external Energy Management Unit (EMU) to increase the supply voltage for that voltage island. If the process is running faster than required, the APC can communicate a reduction in supply voltage until the process performance aligns with the required timing. Like the PA example, this is a continuous closed-loop process and can run completely independent of the digital core.
Simply improving the efficiency of a power converter by a few percent may not be the best place to look for significant energy savings. In many cases, a review of the system architecture might yield insight into areas that could benefit from redesign and significantly improve the energy consumption of the system. Also, where it’s applicable, moving functionality back into the analogue domain can reduce power by allowing digital subsystems to sleep while the analogue blocks do the processing. In any event, looking beyond the standard areas for improvement can expose architectural shortcomings and provide opportunities for improved energy efficiency.
Richard F Zarr is the Chief Technologist of PowerWise Solutions at National Semiconductor.
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