Power to the Package
30 November 2009
Graham Robertson of International Rectifier looks at a packaging innovation that improves MOSFET performance and design flexibility.
Engineers tasked with implementing power stages typically look to maximise efficiency while addressing the common engineering challenges of optimising performance and functionality and minimising board space. In applications ranging from power supplies to industrial batteries and high power DC motors to power tools, the power MOSFET has become an essential element in achieving output requirements consistent with these design goals.
Power Density
When it comes to selecting the optimum MOSFETs for a given design, power density is typically near the top of the agenda. In most applications higher power densities improve design flexibility. For example, in designs that require MOSFETs to be configured in parallel for current sharing, higher current devices may help reduce overall component count and associated assembly costs as fewer MOSFETs can be used to handle the same amount of current. Furthermore, increases in power density and, therefore, ability to handle higher currents, make MOSFETs attractive to more rugged applications where increased ‘headroom’ is required to safeguard components and equipment against unwanted transient conditions.
For manufacturers of power MOSFETs the two main ways to deliver continual power density improvements come through advances in the underlying semiconductor technology and the approach taken to package design. The evolution from planar to ever more advanced trench semiconductor processes, for example, is supporting significant reductions in unit area on resistance (RDS(ON)), with the on resistance of silicon dice achieving increasingly lower levels of RDS(ON). Such reductions, in turn, result in lower power loss and improved thermal performance and can allow vendors to drive up density. However, as semiconductor processes become more mature, ever more focus is being given to realising improvements through packaging innovation.
Package Innovation
Traditionally package limitations have been a significant barrier to improving power density. However, recent advances mean that even mature JEDEC package formats originally intended for DC currents of just tens of Amps are now able to carry hundreds of Amps. For example, International Rectifier has been able to achieve improvements to standard package current handling in the region of 120A.
The major limits on the ability of a package to handle ever higher currents relate to temperature, and a significant part of the advances in package performance have been made possible by looking at the impact of temperature in three different areas. The most obvious and most important one is the silicon junction temperature. For continuous currents, the RDS(ON) of the device will determine the junction temperature as a result of I2R Joule heating. The lower on-resistance of modern silicon allows more current and less heat due to conductive losses.
However, while junction temperature has historically been the main basis for setting current limits, there are two other aspects of temperature to consider (See Figure 1).
The first is the temperatures of the internal wire bonds, which, in some TO-220 packages, can contribute to as much as 30% of overall package on resistance. This percentage is poised to increase as silicon resistances fall further. The second is the temperature at the contact point between the package leads and the substrate (typically a PCB). Techniques for keeping these temperatures as low as possible are playing a key role in increasing both the performance and the long-term reliability of new and emerging MOSFET devices.
Benchmark MOSFETs
To understand how such packaging developments are influencing MOSFET power density, consider International Rectifier’s latest range of HEXFET power MOSFETs. Designed for voltages from 40V to 200V, this range of industrial grade MOSFETs features devices in TO-220 and D2PAK packages that are capable of handling typical currents (at 25ºC) of up to 195A. This in itself represents a 60% improvement over the current ratings typically associated with these mature package types. However, package advances have also allowed the company to develop a new 7-pin D2PAK surface mount package option, which uses proprietary packaging technology to achieve further improvements and deliver current ratings of 240A without size or performance penalties.
MOSFET design considerations
Increases in power density and functionality have helped to provide greater flexibility when it comes to modern MOSFET-based power design. At the same time, choosing the optimum technology for a given design has been further simplified as MOSFET vendors have recognised the need to develop more application-specific devices that address the different requirements of target designs ranging from motor drives to synchronous rectification.
However, there are still many important issues that the design engineer must consider when comparing power MOSFETs. Total losses, for example, are made up of both conduction losses and switching losses and lowering one tends to increase the other. It is, therefore, important to understand how the trade-off between the two will impact the design to effectively select which devices to use.
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