Power breakthrough in memory initiative
25 January 2010
Back in the March 2009, we covered the launch of a new initiative for high-bandwidth, low-power memory interface technology for mobile memory systems. Several months down the line and EPD can report that progress is being made.
Rambus, a technology licensing company specialising in high-speed memory architectures, has achieved a new breakthrough level of power efficiency with its latest silicon test vehicle developed through its Mobile Memory Initiative (MMI). The latest silicon-validated results demonstrate that through the use of MMI innovations, a high-bandwidth mobile memory controller can achieve a power efficiency of 2.2 mW/Gbps. This is a one third improvement over the initial MMI silicon and significantly better than the estimated 10 mW/Gbps of an LPDDR2 400 memory controller.
Launched in February 2009, Rambus’ MMI focuses on achieving high bandwidth at extremely low power to enable advanced applications in next-generation smartphones, netbooks, portable gaming and portable media products. Operating at 4.3 Gbps, a memory system using MMI innovations can deliver over 17 GB/s of memory bandwidth from a single mobile DRAM device.
“The performance demands of next-generation mobile devices are vastly outstripping the pace of battery technology improvements,” said Martin Scott, senior vice president of Research and Technology Development at Rambus. “With the innovations developed through our Mobile Memory Initiative, we can deliver advanced applications and maintain long battery life through our breakthroughs in both bandwidth performance and power efficiency.”
Rambus’ MMI encompasses key innovations based on its signaling and memory architecture expertise, including Very Low-Swing Differential Signaling, FlexClocking Architecture, and Advanced Power State Management. In addition, Rambus’ FlexPhase and Microthreading technologies greatly improve the power efficiencies of mobile platforms.
Dr Judy Chen presented the company’s approach to mobile memory challenges in her paper to the ARM TechCon3 in October in Santa Clara. Her presentation, entitled “Is Mobile Memory Becoming the New Power Hog?” focussed on memory system performance, power, form factor and associated cost, outlining ways to address the issues of scalability, power efficiency, power state exit latency, clock recovery, signal integrity and low-cost packaging used to produce a memory architecture that is optimal for the mobile market.
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