28nm FPGAs
20 April 2010
Stratix V FPGAs break through the bandwidth barrier while lowering system power and cost.
Altera has just revealed its next-generation 28nm Stratix V FPGA family, the industry's highest bandwidth FPGA.
Offering up to 1.6 Tbps of serial switching capability, Stratix V FPGAs use a myriad of new technologies and a 28nm process to reduce the cost and power of high-bandwidth applications.
Manufactured on TSMC's 28nm high-performance process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53Mbits of embedded memory, 3680 18x18 multipliers, and integrated transceivers operating up to an industry-leading 28Gbps.
The devices also incorporate the industry's highest level of application-targeted hard intellectual property for increased system integration and performance without the cost and power penalty. The family includes four variants that address a range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets.
These variants include:
• Stratix V GT FPGA – The industry’s only FPGA with integrated 28Gbps transceivers targeting 100G systems and beyond
• Stratix V GX FPGA – Supports a range of applications with 600Mbps to 12.5Gbps transceivers
• Stratix V GS FPGA – Optimised for high-performance digital signal processing (DSP) applications with 600Mbps to 12.5-Gbps transceivers
• Stratix V E FPGA – Highest density FPGA ideal for ASIC prototyping, emulation or high performance computing applications
Stratix V GX and Stratix V GS FPGAs feature up to 66 high-performance, low-power transceivers operating up to 12.5Gbps. Stratix V FPGAs support and meet compliance for a multitude of 3G, 6G and 10G protocols and electrical standards such as 10G/40G/100G, Interlaken and PCI Express, Gen 3, Gen2, and Gen 1. The devices also provide direct interoperability to 10G backplanes (10GBASE-KR) and optical modules. Stratix V GT FPGA's 28Gbps transceivers are designed to meet the CEI-28G specification. The 28Gbps transceivers consume only 200mW per channel, dramatically reducing a system's power-per-bandwidth profile.
In addition to transceiver bandwidth, Stratix V FPGAs include a 7 x 72bit 1600Mbps DDR3 memory interface and LVDS channels capable of operating at 1.6Gbps on ubiquitous I/Os.
Altera made several enhancements to the Stratix V FPGA's core architecture to increase area and logic efficiency and system performance, including:
• New adaptive logic module (ALM) architecture – adds up to 800K additional registers in the largest device to maximise logic efficiency. The ALM architecture is ideal for heavily pipelined and register-rich designs
• Enhanced embedded memory structure featuring M20K blocks – offers improved area efficiency and higher performance
• Industry's first variable-precision DSP block, which provides the highest efficiency and performance across multiple-precision DSP data paths
• User friendly partial reconfiguration, allowing designers to reconfigure part of the FPGA while other sections remain running
Altera expects to begin shipping samples of Stratix V FPGAs in Q1 2011. Stratix V FPGA will be supported with Quartus II version 10.0 in Q2 2010.
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