Best blend for power design
21 April 2010
Blending MOSFET packaging and silicon advances can simultaneously boost efficiency and power density, according to Graham Robertson.
Room for Improvement
Designers of power modules are responding to these demands by employing more efficient topologies and switching schemes, such as synchronous rectification, which manages the main power-control MOSFET more efficiently compared to a MOSFET/diode combination. Synchronous rectifiers are now finding applications in a wide range of power ratings, from board level Point of load (POL) regulators to DC-to-DC converters above 200W.
To maximise synchronous rectifier efficiency, MOSFETs are individually optimised for use either as the sync FET or as the control FET. Generally speaking, the control FET is optimised for low switching loss, since the device is usually turned on throughout a relatively short duty cycle while the majority of losses occur as the device is operated under hard switching conditions.
Conversely, the majority of sync FET losses occur when the device is turned on, implying demand for low on-state resistance (RDS(ON)). However, the design of each MOSFET must also take into account other loss mechanisms such as Cdv/dt-induced turn on of the sync FET and inductive effects at the control FET’s gate, particularly at higher operating frequencies. Moreover, since the entire load current passes through the sync FET’s body diode at the beginning of each turn-on cycle, these losses can be reduced by integrating a Schottky reverse recovery diode with the sync FET. IR’s FETky devices integrate such a diode.
Figure 1 shows how the efficiency of a synchronous rectifier varies with load current, for a given input and output voltage and switching frequency. The peak efficiency can be increased by reducing the control FET gate charge (Qg), gate resistance (Rg) and RDS(ON). On the other hand, the full-load efficiency is increased by reducing QG and RDS(ON) of the sync FET and by techniques such as FETky integration to combat the body diode losses.
In low-voltage motor-drive applications, the relatively low switching losses incurred in a MOSFET make these the device of choice compared to alternatives such as IGBTs. Although IGBTs have held sway at higher voltages, MOSFETs engineered for low RDS(ON) now provide a more efficient alternative in many cases. It is critical to achieve a low RDS(ON), since conduction losses are defined by I2 x RDS(ON).
In power-conversion applications such as these, demand for miniaturisation brings a general desire to specify higher switching frequencies, which enable designers to specify small values for external inductive and capacitive filtering components. To support fast switching, with low losses, the MOSFET must have a low stored charge, and careful management of the MOSFET capacitance is required.
In power-ORing circuits, MOSFETs are frequently used in preference to simple diodes, to increase efficiency and support more versatile power control. Power ORing using MOSFETs protects power systems where multiple supplies may be used to achieve a level of redundancy, or where more than one power source is required to feed the system. Examples include notebook PCs, which are able to switch from line power to battery power instantaneously with no user involvement. ORing is also deployed in systems where hot-plug capability is required, such as in high-availability telecom equipment. Here, the ORing circuitry protects individual line-replaceable units from power fluctuations and can be used to help ensure the correct sequencing of power to newly inserted cards, or when a power supply card is replaced. Again, low MOSFET RDS(ON) is a pre-requisite to minimise power losses.
Depending on the customer’s preferred safety margin, equipment operating from a 12V DC supply such as board-level POL converters and some synchronous rectifiers and power-ORing networks, will require MOSFETs rated to 25 V or 30 V. For higher voltage power ORing and other applications such as industrial motor drives, synchronous rectifiers and telecom power supplies, voltage ratings from 40 V up to 100 V, 150 V or 200 V may be required.
Improving MOSFET Silicon
Intuitively, increasing the silicon area of the MOSFET serves to reduce RDS(ON). However, the size of the device will also increase. A larger silicon area also results in a high stored charge, leading to poor switching performance and substantial gatedriver losses. Innovations such as Trench technology achieves a favourable combination of low RDS(ON) without storing excessive charge. This can unlock valuable efficiency gains, but circuit designers must also take into account the specific requirements of their application. In a synchronous rectifier, for example, the sync FET must also have a low gate-to-drain charge (Qgd) and a low charge ratio (Qgd/Qgs1) to avoid spurious turn-on of the device and associated Cdv/dt losses.
Other techniques to limit switching losses, especially in hard-switching applications such as the synchronous rectifier control FET, include optimisation of the gate dimensions and process technology to minimise the gate resistance (Rg).
Surface-Mount Power Packaging
Advancements in MOSFET silicon have delivered substantial improvements in device performance. However, to deliver further performance improvements and efficiency gains at the same time as supporting ongoing product miniaturisation, the bestperforming silicon must be teamed with package innovations that successfully minimises losses, maximises heat dissipation, and reduces overall footprint.
The evolution of power packages has long prioritised reduction of Die-Free Package Resistance (DFPR) and improvement in thermal performance. Enhanced power packages matching the popular SO-8 footprint have already used techniques such as increasing the cross-sectional area of drain and source connections, and providing efficient mechanisms to conduct heat away from the die and into the PCB. One example is PowerPak, which exposes the drain terminal to allow direct soldering to the PCB.
Another high-performance power package technology, DirectFET, flips the die and enables the gate, source and drain to be soldered to heat spreaders on the board. IR has DirectFET devices with die free package resistance as low as 0.15 mΩ, inductance less than 0.1 mH, and junction-to-case thermal resistance to less than 1°C/W for the gate and source connections, and 1.4°C/W for the drain.
To increase efficiency and power density still further, smaller surface-mount package styles delivering high thermal and electrical performance are required.
Taking it to the Next Level
The Power Quad Flat No-lead (PQFN) package has been developed to meet these demands. The electrical contacts are implemented on the underside of the package, to minimise the footprint in relation to the MOSFET die size.
The drain connection is implemented as a large thermal pad, which maximises heat transfer into the PCB. This large drain also helps to minimise the package DFPR, in conjunction with multiple source contacts (figure 3).
Internally, a thick copper leadframe and aluminium bondwires provide the major interconnections, as shown in figure 4. The package is assembled using a solder diefixing process in combination with clip fixing featuring an optimised copper clip. Together, these features maximise electrical and thermal performance within small surfacemount form factors. PQFN was conceived to support a variety of size options from 2 x 2 mm to 12 x 12 mm.
This package technology serves to maximise the advantages of silicon-level innovations aimed at enhancing power density, efficiency and reliability.
Next-Generation Performance Parameters
IR recently announced a series of PQFNpackaged MOSFETs in voltage ratings from 25 V and 30 V for point-of-load regulation through to 150 V and 200 V devices targeting higher-power synchronous rectification, ORing and motor-control applications.
Among these, the 25V IRFH5250DTRPBF has RDS(ON) of 1.7 mΩ (at Vgs = 4.5 V) and 39 nC gate charge, and also features an integrated Schottky reverse-recovery diode (FETky device) making it suitable for sync FET duties in synchronous rectifier modules. It is housed in a 5 x 6 x 0.2 mm PQFN package.
For use as a control FET at the same voltage level, the IRFH5255TRPBF is optimised for even lower Qg of 7 nC, has 8.8 mΩ RDS(ON), and has low gate resistance. In addition to helping enhance the devices’ electrical performance parameters, the PQFN package is also the major factor contributing to junction-to-case thermal resistance of better than 0.5 °C/W enabling efficient heat removal to boost reliability.
Conclusion
Combining the PQFN package with enhancements to MOSFET silicon that improve the trade-off between on-state and switching performance enables power supply designers to miniaturise energy-efficient new designs by taking advantage of the smaller package outline, smaller external
components, and increased current-handling capability.
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