28-nm FPGA family are ‘built for bandwidth’
28 May 2010
Altera claims its next generation 28-nm Stratix V FPGA family has the industry's highest bandwidth.
Offering up to 1.6 Tbps of serial switching capability, Stratix V FPGAs leverage a myriad of new technologies and a leading-edge 28-nm process to reduce the cost and power of high-bandwidth applications, including communications, broadcast, military and computing.
The new family will be available from Q1 2011 with the development tools available in the coming few months. Manufactured on TSMC's 28 nm High-Performance (HP) process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18x18 multipliers and integrated transceivers operating up to an 28 Gbps. The devices also incorporate the industry's highest level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty.
Stratix V GX and Stratix V GS FPGAs feature up to 66 high-performance, lowpower transceivers operating up to 12.5 Gbps. Stratix V FPGAs support and meet compliance for a multitude of 3G, 6G and 10G protocols and electrical standards such as 10G/40G/100G, Interlaken and PCI Express, Gen 3, Gen2, Gen 1. The devices also provide direct interoperability to 10G backplanes (10GBASE-KR) and optical modules. Stratix V GT FPGA's 28-Gbps transceivers are designed to meet the CEI-28G specification. The 28-Gbps transceivers consume only 200 mW per channel, dramatically reducing a system's power-per-bandwidth profile.
Stratix V FPGAs include the highest level of hard IP integration on any FPGA, increasing the device's capabilities without incurring a power or cost penalty. Hardened functions in the device include PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI/OBSAI, Interlaken, Serial RapidIO (SRIO) 2.0 and 10 Gigabit Ethernet (GbE) 10GBASE-R. Memory interfaces with hardened read/write paths include DDR3, RLDRAM II and QDR II+.
Stratix V FPGAs feature the company's Embedded HardCopy Blocks. This methodology gives Altera the ability to quickly change hardened functions within the FPGA, enabling the development of application-targeted device variants in three to six months. Embedded HardCopy Blocks provide
customers with the equivalent of 700K additional LEs with 65% lower power compared to a soft logic implementation.
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