Time gives logic new dimension
28 May 2010
Tabula has introduced Spacetime, a 3-dimensional programmable logic architecture that uses time as its third dimension.
Tabula achieves this by combining the Spacetime hardware that dynamically reconfigures logic, memory, and interconnect at multi-GHz rates with the Spacetime compiler that manages this rapid reconfiguration transparently. Tabula will leverage Spacetime to deliver 3-D devices that have density advantages and shorter interconnects when compared to FPGAs that use 2D architectures. In addition, Tabula will deliver these benefits while preserving a traditional design methodology. As a result, claims Tabula, Spacetime will enable a new class of programmable devices that combines the capability of an ASIC with the ease of use of an FPGA at price points suitable for volume production.
“The key to Spacetime and its many advantages is resolving the interconnect problem intrinsic to FPGAs,” said Steve Teig, Tabula’s President and CTO. “Almost 90% of the core area of FPGAs is devoted to the implementation and control of interconnect. Besides driving up die size and product cost, Agilent has introduced what it claims to be the world’s fastest real time oscilloscope, The Infiniium 9000 X-Series includes ten models in the ‘true analogue’ bandwidth range from 16 GHz to 32 GHz and feature the lowest noise and have the lowest jitter measurement floor in the industry.
The accompanying probing system offers browsing to 30 GHz with a full range of accessories rated to 28 GHz and the ability to upgrade bandwidth in the future. In addition, the 90000 X-Series scopes offer more than 40 measurement-specific application packages including jitter, triggering, measurement, and analysis tools and full compliance certification test suites.
Engineers working with high-energy physics, emerging wireline communication standards, and high-speed serial data links, such as USB, SAS, or PCI Express, will be interested in these oscilloscopes to capture fast, singleshot events and to make critical measurements like jitter while ensuring compliance to industry standards for interoperability. With data rates in the next few years extending beyond 10 Gbps, engineers need oscilloscopes that can deliver higher-bandwidth measurements.
Agilent invested in a proprietary indium phosphide (InP) integrated circuit process to enable high-frequency capability while yielding the industry’s lowest noise floor and jitter measurement floor. Custom aluminum nitride packaging technology combines five InP chips in the front-end multichip module which incorporates unique noise shielding and heat dissipation techniques. the long connections also limit performance and make timing closure more difficult. If you’re going to achieve a breakthrough in programmable capability and affordability, you have to make the interconnect more efficient, and that’s what Spacetime does.”
Tabula has over 80 patents granted around the Spacetime architecture with over 70 more pending. Tabula is developing a family of general-purpose 3PLD devices that are based on the Spacetime architecture. Tabula will initially target the programmable logic market but will also extend the benefits of programmability into markets that FPGAs cannot serve cost-effectively.
"Tabula's Spacetime technology is a real innovation, not just hype," said Tom R. Halfhill, Senior Analyst for In-Stat's Microprocessor Report. "By rapidly reconfiguring their programmable-logic fabric -- up to 1.6 billion times per second -- Tabula's chips can use the same logic gates and wires over and over again for different purposes. To developers, the fabric looks much larger than it really is, without paying for additional silicon and power. Perhaps the biggest innovation is that Tabula's development tools hide the details of rapid reconfiguration from developers and users. Tabula's 3PLDs have only one die, but they emulate a three-dimensional PLD that stacks multiple chips in a single package."
The first family to employ the Spacetime technology is the ABAX family of 3D Programmable Logic Devices. Deployed on TSMC’s 40 nm process, ABAX devices integrate a mixture of fully configurable, high performance I/Os, including 920 general purpose parallel I/Os, and 48 x 6.5Gbps serial transceivers. To improve time to market and productivity, the ABAX family’s design flow closely resembles those for FPGAs and ASICs, using synthesis, placement, and routing to compile designs from RTL into silicon. In addition, ABAX devices support a broad portfolio of soft IP cores, including DDR2 and DDR3 memory controllers, PCI Express, Gigabit and 10 Gigabit Ethernet, soft CPUs, sRIO, CPRI, and OBSAI.
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