Bridging the technology gap
28 May 2010
FPGAs present a significant opportunity in PCI Express connectivity as Greg Lara discusses.
The embedded industry is exhibiting widespread adoption of the PCI Express protocol, following its introduction by Intel to the PCI SIG (Special Interest Group) in 2004. Initially developed to provide the next generation interconnect architecture for personal computing, its many benefits have resonated within the embedded industry too, by addressing many of the same issues.
While the PC industry is dominated by a single architecture, the embedded sector still supports a large number of alternative processor platforms, but there is evidence to suggest this fragmentation is reducing, partly through the use of common interfaces such as PCI Express. Through this high speed, high performance and highly regulated standard it is possible to create hardware platforms with common interfaces, allowing greater ‘plug and play’ between peripherals. In addition, the relative dominance of IP providers such as MIPS and ARM means general purpose hardware platforms can be easily created which offer high performance at low cost. The ARM Cortex-M3 is a prime example, as it is equally capable across a wide range of applications where microcontrollers may have previously been used, such as networking or industrial control.
The ubiquity of the PCI Express protocol is now extending to the ultimate in general purpose co-processing; the FPGA. Its ability to provide customised hardware for protocol bridging, hardware acceleration and embedded control has made it the ideal complementary technology to general purpose processor platforms. As Figure 1 shows, the incorporation of an FPGA into an Intel Atom based hardware platform enables a high performance, low power general purpose computing system that is suitable for any number of non-PC application areas.
Serial displaces parallel
With the vast array of interface protocols available, it’s worth reviewing why PCI Express has risen to its dominant position in such a short time. The development of packet based serial communication started within the highly demanding telecommunications sector, to create high bandwidth links capable of operating over long distances. These serial buses rapidly developed to also provide shorter range communications between closely located equipment, as well as components on boards or over backplanes. The clocks embedded within serial buses present a more robust and reliable solution to parallel buses and it wasn’t long before they were integrated in to leading high-end FPGAs used extensively within the communications sector.
The ascension of serial I/O has overcome the perception that it is a complex technology suitable only for high end systems. Initially this may have been justified but today most systems exhibit performance requirements that demand serial interconnect, and in response to this demand FPGA vendors are now integrating serial transceivers into low cost FPGAs in order to make their implementation even easier.
The latest and, perhaps, greatest serial bus to date is PCI Express. Intel’s intention was to develop a high bandwidth bus that overcame the limitations of a shared bus architecture, such as skew and bus contention. The base specification for version 1.1 of this point-to-point serial solution delivers 2.5 Gbit/s which, when factoring in the standard’s 8b10b coding scheme, yields a theoretical maximum data rate of 2.0 Gbit/s, or 250 Mbyte/s. For higher bandwidth, base specifications v2.0 and v3.0 offer 5.0 Gbit/s and 8.0 Gbit/s respectively. The standard also allows for multi-lane communications, however most embedded applications find that a single-lane PCI Express v1.1 link delivers a viable bandwidth versus power trade-off.
Its high bandwidth and small form-factor have made PCI Express a logical choice for chip-to-chip communications. Since integrating PCI Express technology at the silicon level, this has become particularly relevant for processor-to-FPGA communications. Demonstrating this, a new class of low cost FPGAs now integrate PCI Express serial transceivers, enabling cost effective implementation of the serial link between low power devices targeting embedded applications such as bridging the gap between back-office PCs with factory floor equipment.
Seamless communication
It is the use of PCI Express that creates this seamless flow of data between enterprise networks and industrial automation systems. This level of connectivity allows low cost FPGAs to implement the latest real time industrial networking protocols, such as EtherCAT, PROFINET, SERCOS III and Ethernet Powerlink, to deliver deterministic, process critical communications for complex, interconnected manufacturing cells in the factory floor.
Often these applications require advanced motor control solutions, which are easily implemented using hardware accelerators in an FPGA. This enables the efficient implementation of complex algorithms such as real time observers, inverse modelling, Kalman filters and sensorless field-oriented control, as used in motor and motion control systems.
A major benefit of FPGA devices is their ability to integrate hardcores, such as serial transceivers, with soft logic needed to implement the physical, data and transaction layers. Until recently these high performance serial transceivers could only be found on high end FPGAs but technological developments mean it is now cost effective to integrate these same transceivers in low cost FPGAs. Coupled with the flexibility of FPGA technology, this opens up a new world of possibilities, in the form of high performance off-load engines and peripherals, which can now be closely coupled to a host processor over a high performance PCI Express link.
For example, the low cost Spartan-6 LXT family from Xilinx features integrated PCI Express connectivity in an FPGA fabric capable of delivering powerful co-processor functions, such as hardware-acceleration for compute-intensive functions (Figure 2). These devices integrate low power GTP transceivers with a PCI Express endpoint implemented as hard IP, providing one lane (x1) Gen 1 connectivity. By implementing the PCI Express endpoint block as hard IP, it frees up approximately 7000 logic cells that would have otherwise been needed to implement the endpoint block.
Furthermore, by integrating the PCI Express endpoint as hard IP, as opposed to soft IP, which consumes resources within the FPGA’s programmable fabric, this high performance serial communications technology becomes even more cost effective to implement, extending its reach to the very lowest priced FPGA devices. While it is true that IP implemented at the hardware level is less flexible than programmable logic, Xilinx has been careful to preserve configurability. Parameters such as maximum payload size, reference clock frequency, base address register decoding and filtering, and more, can be configured using Xilinx’ development tools. These generate the files necessary to complete the endpoint design, by setting the configurable capabilities to the values required by the application, as well as setting the clocking resources, memory buffers and interface needs of the application-specific aspects of the endpoint’s function.
Designing with PCI Express
Xilinx ISE Design Suite, which supports the Spartan-6 family, provides the perfect solution to managing this configuration process. It aids designers by automatically generating customised LogiCORE IP for configuring the PCI Express endpoint interface the CORE Generator tool features a graphical user interface (GUI) to make it even simpler to configure endpoint parameters. It also helps in setting up the necessary RAM and buffers, as well as clock resources, while preparing the interface for the application specific part of the PCI Express endpoint design (Figure 3). The ChipScope Pro Serial I/O Toolkit helps evaluate link performance, allowing the design to be fine tuned through the adjustable EQ setting of the GTP transceiver.
This approach is being complemented by the introduction of more advanced Targeted Reference Designs; bringing the same benefits processor manufacturers bestow upon software developers, to FPGA users. These reference designs bring all the benefits of integrated hardcores and automatically generated configuration files, to application-specific sectors which have previously been unable to leverage the benefits of high performance serial communication.
Targeted Reference Designs combine all the resources developers need to evaluate the capabilities of the FPGAs in terms of their hardwired silicon resources and programmable fabric. They are also intended to provide a launching point for application development, such as the Connectivity Targeted Reference Design. This is a fully operational bridge between the Gigabit Ethernet and PCI Express protocols, providing an evaluation platform which fully exercises the features of the Spartan-6 LXT including the GTP transceivers, the PCI Express Endpoint block and the DDR/DDR2/DDR3 SDRAMs and LPDDR memory controller block.
Each reference design is provided with all source code, implementation scripts and other software (drivers, APIs), along with documentation, to enable a development team to quickly adopt and start designing with PCI Express-enabled FPGAs. The Connectivity Targeted Reference Design also integrates a number of other IP cores, including a bus mastering packet DMA engine developed by Xilinx Alliance Program member, Northwest Logic, as well as the Xilinx Platform Studio Local Link Tri-Mode Ethernet MAC (XPS-LL-TEMAC). The DMA engine works in conjunction with the integrated endpoint block for PCI Express, to off-load processor data transfer overhead. This enables high speed data movement between the system memory and the FPGA. The PCI Express endpoint block provides an interface to the host system while the Gigabit Ethernet is used as a network interface card.
To accelerate the development process further, Xilinx has developed the SP605 evaluation board. It includes a PCI Express edge connector, which makes it easier to connect the board to a PC and start evaluating quickly, even to the point of creating a customised application. The SP605 also features an FPGA Mezzanine Card (FMC) connector, providing further extensibility using daughter cards provided either by Xilinx of a Third Party partner.
Another benefit of choosing a solution with fully integrated PCI Express capability is compatibility. Xilinx has verified the Spartan-6 LXT family to the v1.1 base specification at compliance workshops hosted by the PCI-SIG, and the Spartan-6 LXT and its related SP605 evaluation board are now included in the PCI Express Integrators List.
The demand for high speed, high performance serial I/O in the telecommunications sector has helped manufacturers of integrated devices overcome a crucial commercial barrier, such that it is now cost effective to implement transceivers in low cost FPGA devices. This commercial breakthrough is enabled by technological achievements in the design and manufacture of configurable logic and by strategically combining the benefits of hard IP with the flexibility of an FPGA fabric, many more application areas are now able to leverage the benefits of PCI Express.
As this advanced yet still relatively young protocol develops it will bring further benefits to the embedded sector, allowing more sophisticated systems to be built which are able to communicate from the component level through to the enterprise. This ubiquitous connectivity has never before been commercially or technologically viable and is only now possible thanks to the market’s commitment to a common bus architecture. The future of PCI Express will see faster bandwidths, offering even greater possibilities to systems integrators.
Greg Lara is Marketing Manger for Xilinx
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