16 bit 125 Msps ADCs reduce power to 185 mW
01 February 2011
Linear’s families of low power ADCs dissipate around half the power of other 16 bit solutions.
The LTC2165 and LTC2185 families are single and two-channel simultaneous sampling parallel ADCs offering a choice of full-rate CMOS, or double data rate (DDR) CMOS/LVDS digital outputs with programmable digital output timing, programmable LVDS output current and optional LVDS output termination.
The LTC2195 family includes two-channel, simultaneous sampling ADCs with serial LVDS outputs.
Each ADC family offers a choice of pin-compatible converters, sampling from 25 Msps up to 125 Msps and optimised for the lowest power dissipation at the rated speed. They include popular features such as Linear Technology’s digital output randomiser and alternate bit polarity (ABP) mode that minimise digital feedback.
These low power 16 bit ADCs enable designers to upgrade performance while maintaining portability in applications such as handheld test and instrumentation, radar/LIDAR, portable medical imaging, PET/SPECT scanners, smart antenna systems and a variety of low-power communication systems.
The dual LTC2185/LTC2195 and single LTC2165 consume 185 mW/channel at 125 Msps and offer signal to noise ratio (SNR) performance of 76.8 dB and SFDR of 9 0dB at baseband. Pin-compatible speed grade options include 25 Msps, 40 Msps, 65 Msps, 80 Msps and 105 Msps with approximate power dissipation of just 1.5mW/Msps per channel.
Further power savings can be achieved by placing the devices in standby (20mW) or shutdown (1mW). Analogue full power bandwidth of 550MHz and ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance.
Available in compact QFN packages, designers can benefit from the flexible choice of interfaces that minimise pin count and ease routing to FPGAs.
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