New solution eases IEEE 1588v2 integration
26 September 2011
When the original IEEE 1588 standard was introduced it didn’t anticipate the growing popularity of highly synchronised distributed systems.
Many applications are dependent on signals arriving from different areas of the network, and different network topologies for time critical processing. This need prompted the IEEE to formulate a second iteration of the standard.
IEEE 1588 v2 includes a transparent clock that modifies timestamps in messages as they pass through the network. This timestamp modification can take account of daisy chaining as well as differing topologies. Provisions are also included for improved ruggedness and accuracy in the system.
The implementation of IEEE 1588 v2 at the moment has generally been constricted to FPGAs, but this has proven large and inefficient. Micrel’s newly launched EtherSync family is intended to provide an integrated solution that reduces host-processing demands. The three members of the family are KSZ8463 3-port switch with MII/RMII interface, KSX8462 3-port switch with generic host interface and KSX8441: IEEE 1588v2, Controller with generic host interface.
The family supports centralised and distributed network topologies. A full complement of Precise Timing Protocol timing modes are provided, including the Transparent Clock (TC) introduced in IEEE 1588v2. By integrating the IEEE 1588 PTPv2 time stamping as close to the physical layer as possible, sub-100ns synchronisation performance has been demonstrated.
Micrel will also offer a pre-qualified Precise Timing Protocol software stack, which has been integrated with the driver and optimised to exploit the KSZ84xx architecture.
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