Editorial archive;
Verification accelerates development (30 July 2010)
A fully integrated verification computing platform, Palladium XP from Cadence, unifies simulation, acceleration and emulation into a single verification environment.
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Addressing productivity crisis for SoC design (11 May 2010)
Cadence Design Systems has released Cadence Encounter Digital Implementation (EDI) System 9.1.
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Solve the routing bottleneck (20 July 2009)
Hitachi cuts place-and-route design time by 40% using Cadence design software for PCBs.
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Function better with power predictability (01 September 2007)
In today’s process geometries, power consumption has become a factor that must be managed in all chip designs. For many types of chips, such as plugged-in applications, this is a new challenge
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What makes a 45nm material world? (01 July 2007)
There could be 45nm silicon widely available by the next quarter. CAROLINE HAYES reports on the material changes that will bring this about, from high-k materials to photo mask printing
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Verification addresses low-power logic (01 April 2007)
As more portable devices need a longer battery life, the need to make power savings is moving to integrated, high-performance, 90nm and below silicon. The lower processes can create heat management issues, which can be resolved by optimising power throughout the chip, writes TOM BRESLIN.
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Cadence lays out holistic approach (01 August 2006)
In today’s design world, there is an increasing integration of RF and mixed signal design with hardware and software integration. These bring technology risks; experimenting with technology under time and budget constraints and make demands on performance and power consumption objectives. Mike Fister, president and CEO Cadence Design Systems identified a holistic approach to the development cycle, at CDNLive! (Cadence Designer Network) conference, last month.
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